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4. Communication between PLD IC8001 and Real Time Clock IC4101
When the time data is to be set, Main System Controller IC6005 outputs the time setup data to Real Time Clock IC4101 from pin-58 [MULTI_SO] in synchronization
with the clock of pin-4[EX_MULTI_SCK] and chip enable signal of pin-20 [RTC_CE] of PLD IC8001. During the time data read, Main System Controller IC6005 outputs
the data read command to Real Time Clock IC4101 in the same manner as the time data writing. When the Real Time Clock IC4101 receives the read command, it
outputs the time data to PLD IC8001 from pin-1 [SIO]. PLD IC8001 thus receives the time information. (Main System Controller IC6005 receives the time information
through the serial communication between IC6005 and IC8001.)
with the clock of pin-4[EX_MULTI_SCK] and chip enable signal of pin-20 [RTC_CE] of PLD IC8001. During the time data read, Main System Controller IC6005 outputs
the data read command to Real Time Clock IC4101 in the same manner as the time data writing. When the Real Time Clock IC4101 receives the read command, it
outputs the time data to PLD IC8001 from pin-1 [SIO]. PLD IC8001 thus receives the time information. (Main System Controller IC6005 receives the time information
through the serial communication between IC6005 and IC8001.)
When the unit is in the sleep mode, Real Time Clock IC4101 works by the VB voltage supplied to pin-4 [VSB] and keeps counting the time information.
5. Communication between PLD IC8001 and D/A CONVERTER IC3002
To control D/A CONVERTER IC3002, PLD IC8001 outputs the serial data from pin-11 [EX_MULTI_SO] in synchronization with the clock of pin-4 [EX_MULTI_SCK] and
the chip select signal of pin-18 [DAC_XCS]. The D/A CONVERTER IC3002 starts operation according to the input commands when the chip select signal becomes “L”.
The main interfaces are described below.
Internal Reset
Mute Control
Volume Control
Setting of Sampling Frequency (Always 44.1 [kHz] in the unit) etc.
the chip select signal of pin-18 [DAC_XCS]. The D/A CONVERTER IC3002 starts operation according to the input commands when the chip select signal becomes “L”.
The main interfaces are described below.
Internal Reset
Mute Control
Volume Control
Setting of Sampling Frequency (Always 44.1 [kHz] in the unit) etc.
6. Communication between PLD IC8001 and OEL Block
To control the display of OEL Module, PLD IC8001 outputs the display data from pin-11 [EX_MULTI_SO] in synchronization with the clock of pin-4 [EX_MULTI_SCK]
and the chip select signal of pin-12 [LCD_XCS].
and the chip select signal of pin-12 [LCD_XCS].
7. Communication between PLD IC8001 and Cradle
Not available at the present. (This communication lines are prepared in the future.)
8. Communication between USB CONTROLLER IC5001 and PC
The unit has the USB terminal to communicate with PC. USB CONTROLLER IC5001 performs the data communication with PC through the following input / output
terminals.
USB CONTROLLER IC5001 Pin-10 [DM] (D-)
USB CONTROLLER IC5001 Pin-8 [DP] (D+)
terminals.
USB CONTROLLER IC5001 Pin-10 [DM] (D-)
USB CONTROLLER IC5001 Pin-8 [DP] (D+)
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