MHC-S9D, ST-S9 - Sony Audio Service Manual (repair manual). Page 17

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ST-S9
17
17
5-7.
SCHEMATIC  DIAGRAM  – DSP Board (2/2) –
 See page 11 for Waveforms. 
 See page 11 for IC Block Diagram.
(Page 16)
(Page 12)
ST-S9
18
18
5-8.
PRINTED  WIRING  BOARDS  – PANEL Section –
 See page 10 for Circuit Boards Location.
FL601
FLUORESCENT
INDICATOR
TUBE
S611
JW45
S610
S604
S605
S609
S608
S606
S607
S601
S602
S603
R620
X601
C608
C607
C606
R628
R629
R630
R607
R632
R604
R634
R631
R636
R633
R638
R635
C601
R603
JW8
JW6
R605
R618
R619
R627
R621
R622
R623
R624
R625
R626
C610
NO601
R637
R617
C652
JW10
R608
R616
CN602
C605
C653
C654
C655
C656
C657
C658
C659
C660
C661
C662
JW3
C651
R639
R606
D601
JW11
JW57
JW31
JW33
JW36
JW24
C649
C650
JW1
JW4
JW601
JW602
R677
JW114
R602
R601
C603
C663
C664
C669
JW5
IC601
NO101
R101
R102
C101
IC101
C665
C666
C615
C614
(AEP, UK)
(AEP, UK)
PANEL BOARD
S601 – 612
ENTER
PRESET
TUNER MEMORY
STEREO/MONO
TUNER/BAND
+
+
TUNING
D
MAIN BOARD
CN502
TIMER SELECT
CLOCK/TIMER
DISPLAY
1
3
1-680-696-
11
(25)
1-680-697-
11
(25)
1
1
3
3
SIRCS
BOARD
A
B
C
D
1
2
3
4
5
6
7
8
9
10
PTY
S612
• Semiconductor
Location
Ref. No.
Location
D601
C-5
IC101
C-10
IC601
B-5
(Page 14)
ST-S9
19
19
5-9.
SCHEMATIC  DIAGRAM  – PANEL Section –
 See page 11 for Waveform.
(Page 13)
ST-S9
20
20
5-10.
IC  PIN  FUNCTION  DESCRIPTION
 MAIN BOARD  IC501 M30622MGA-A77FP (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
AMP-DATA
O
Serial data output to the M61512FP (IC607)
2
AMP-CLK
O
Serial data transfer clock signal output to the M61512FP (IC607)
3
AMP-LAT
O
Serial data latch pulse signal output to the M61512FP (IC607)
4
SIRCS
I
Remote control signal input from the remote control receiver (IC101)
5
DIG-TX
O
Serial data output to the CXD9617R (IC601), digital audio interface receiver (IC604) and digital 
filter (IC606)
6
DSP-RX
I
Serial data input from the digital audio interface receiver (IC604)
7
DIG-CLK
O
Serial data transfer clock signal output to the CXD9617R (IC601), digital audio interface receiver 
(IC604) and digital filter (IC606)
8
GND
Ground terminal
9
CNVSS
Not used
10
XCIN
I
Sub system clock input terminal (32.768 kHz)
11
XCOUT
O
Sub system clock output terminal (32.768 kHz)
12
RESET
I
System reset signal input from the reset signal generator (IC551)    “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
13
XOUT
O
Main system clock output terminal (16 MHz)
14
VSS
Ground terminal
15
XIN
I
Main system clock input terminal (16 MHz)
16
VCC
Power supply terminal (+5V)
17
NMI
I
Non-maskable interrupt input terminal    Fixed at “H” in this set
18
RDS-INT
I
Serial data transfer clock signal input from the RDS decoder on the FM/AM tuner unit
(Used for the AEP and UK models)
19
Not used (open)
20
RDS-DATA
I
Serial data input from the RDS decoder on the FM/AM tuner unit
(Used for the AEP and UK models)
21
ST-MUTE
O
Tuner muting on/off control signal output to the FM/AM tuner unit    “L”: muting on
22
ST-CE
O
Chip enable signal output to the FM/AM tuner unit
23
ST-DOUT
O
Serial data output to the FM/AM tuner unit
24
Not used (open)
25
ST-DIN
I
Serial data input from the FM/AM tuner unit
26
Not used (open)
27
ST-CLK
O
Serial data transfer clock signal output to the FM/AM tuner unit
28
Not used (open)
29
IIC CLK
I/O
Communication data reading clock signal input or transfer clock signal output with the display 
controller (IC601) and DVP-S9
30
IIC DATA
I/O
Communication data bus with the display controller (IC601) and DVP-S9
31 to 34
NO-USE
Not used
35 to 40
Not used (open)
41
M-RESET
O
Reset signal output to the display controller (IC601)    “L”: reset
42 to 50
Not used (open)
51
NO-USE
Not used
52 to 57
Not used (open)
58
EXP-IN DATA
I
Serial data input from the I/O expander in the TA-S9D
59
EXP-OUT DATA
O
Serial data output to the I/O expander in the TA-S9D
60
EXP-LAT
O
Serial data latch pulse signal output to the I/O expander in the TA-S9D
61
EXP-CLK
O
Serial data transfer clock signal output to the I/O expander in the TA-S9D
Pin No.
Pin Name
I/O
Description
62
VCC
Power supply terminal (+5V)
63
SOFT-TEST
O
Soft test output terminal    Not used (open)
64
VSS
Ground terminal
65 to 70
Not used (open)
71
LINE-MUTE
O
Audio line muting on/off control signal output to the audio line circuit    “L”: muting on
72
Not used (open)
73
DISPLAY KEY
I
DISPLAY switch (S601) input terminal
74
POWER KEY
I
Power on/off switch in the TA-S9D input terminal
75
DIR-UNLOCK
I
PLL lock error and data error flag input from the digital audio interface receiver (IC604)
76
DIR-CS
O
Chip enable signal output to the digital audio interface receiver (IC604)
77
DIR-XSTATE
I
Source clock switching monitor input from the digital audio interface receiver (IC604)
78
DIR-RX
I
Read data input from the digital audio interface receiver (IC604)
79
CODEC-SMUTE
O
Soft muting on/off control signal output to the A/D, D/A converter (IC605)    “L”: muting on
80
DSP-ACK
I
Acknowledge signal input from the CXD9617R (IC601)
81
DSP-CS
O
Chip select signal output to the CXD9617R (IC601)
82
DSP-DECODE
I
Decode signal input from the CXD9617R (IC601)
83 to 86
Not used (open)
87
STEREO
I
FM stereo detection signal input from the FM/AM tuner unit    “L”: stereo
88
TUNED
I
Tuning detection signal input from the FM/AM tuner unit    “L”: tuned
89 to 91
Not used (open)
92
MODEL-IN
I
Model setting terminal
93
SPEC-IN
I
Specification setting terminal
94
Not used (open)
95
V-MUTE
O
Video muting on/off control signal output terminal    “L”: muting on    Not used (open)
96
AVSS
Ground terminal
97
Not used (open)
98
VREF
I
Reference voltage (+5V) input terminal
99
AVCC
Power supply terminal (+5V)
100
AC-CUT
I
AC cut on/off detection signal input from the reset signal generator (IC551)
“L”: AC cut on, “H”: AC cut off or checked
21
ST-S9
 DSP  BOARD  IC601  CXD9617R (AUDIO DIGITAL SIGNAL PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
VSS
Ground terminal
2
XRST
I
Reset signal input from the M61512FP (IC607)    “L”: reset
3
EXTIN
I
Master clock signal input terminal    Not used (fixed at “L”)
4
FS2
I
Sampling frequency selection signal input terminal    Not used (fixed at “L”)
5
VDDI
Power supply terminal (+2.6V)
6
FS1
I
Sampling frequency selection signal input terminal    Not used (fixed at “L”)
7
PLOCK
O
Internal PLL lock signal output terminal    Not used (open)
8
VSS
Ground terminal
9
MCLK1
I
Oscillation clock signal input from the digital audio interface receiver (IC604)
10
VDDI
Power supply terminal (+2.6V)
11
VSS
Ground terminal
12
MCLK2
O
Oscillation clock signal output terminal    Not used (open)
13
MS
I
Master/slave selection signal input terminal    “L”: slave, “H”: master (fixed at “L” in this set)
14
SCKOUT
O
Internal system clock signal output to the digital filter (IC606)
15
LRCKI1
I
L/R sampling clock signal (44.1 kHz) input terminal    Not used (open)
16
VDDE
Power supply terminal (+3.3V)
17
BCKI1
I
Bit clock signal (2.8224 MHz) input terminal    Not used (open)
18
SDI1
I
Audio serial data input from the D/A, A/D converter (IC605)
19
LRCKO
O
L/R sampling clock signal (44.1 kHz) output to the D/A, A/D converter (IC605) and digital filter 
(IC606)
20
BCKO
O
Bit clock signal (2.8224 MHz) output to the D/A, A/D converter (IC605) and digital filter (IC606)
21
VSS
Ground terminal
22
KFSIO
I
Audio clock signal input from the digital audio interface receiver (IC604)
23 to 25
SDO1 to SDO3
O
Audio serial data output to the A/D, D/A converter (IC604)
26
SDO4
O
Audio serial data output to the digital filter (IC606)
27
SPDIF
O
S/PDIF signal output terminal    Not used (open)
28
LRCKI2
I
L/R sampling clock signal (44.1 kHz) input from the digital audio interface receiver (IC604)
29
BCKI2
I
Bit clock signal (2.8224 MHz) input from the digital audio interface receiver (IC604)
30
SDI2
I
Audio serial data input from the digital audio interface receiver (IC604)
31
VSS
Ground terminal
32
HACN
O
Acknowledge signal output to the system controller (IC501)
33
HDIN
I
Write data input from the system controller (IC501)
34
HCLK
I
Clock signal input from the system controller (IC501)
35
HDOUT
O
Read data output to the system controller (IC501)
36
HCS
I
Chip select signal input from the system controller (IC501)
37
SDCLK
O
Clock signal output terminal    Not used (open)
38
CLKEN
O
Clock enable signal output terminal    Not used (open)
39
RAS
O
Row address strobe signal output terminal    Not used (open)
40
VDDI
Power supply terminal (+2.6V)
41
VSS
Ground terminal
42
CAS
O
Column address strobe signal output terminal    Not used (open)
43
DQM
O
Output terminal of data input/output mask    Not used (open)
44
CS0
O
Chip select signal output to the S-RAM (IC602)
45
WE0
O
Write enable signal output to the S-RAM (IC602)
46
VDDE
Power supply terminal (+3.3V)
47
WMD1
I
S-RAM wait mode setting terminal    Fixed at “H” in this set
22
ST-S9
Pin No.
Pin Name
I/O
Description
48
VSS
Ground terminal
49
WMD0
I
S-RAM wait mode setting terminal    Fixed at “L” in this set
50
PAGE2
O
Page selection signal output terminal    Not used (open)
51
VSS
Ground terminal
52, 53
PAGE1, PAGE0
O
Page selection signal output terminal    Not used (open)
54
BOOT
I
Boot mode control signal input terminal    Not used (fixed at “L”)
55
BTACT
O
Boot mode state display signal output terminal    Not used (open)
56
BST
I
Boot trap signal input from the M61512FP (IC607)
57
MOD1
I
PLL input frequency select terminal     “L”: 384fs, “H”: 256fs (fixed at “H” in this set)
58
MOD0
I
Mode setting terminal     “L”: single chip mode, “H”: use prohibition (fixed at “L” in this set)
59
EXLOCK
I
PLL lock error and data error flag input from the digital audio interface receiver (IC604)
60
VDDI
Power supply terminal (+2.6V)
61
VSS
Ground terminal
62, 63
A17, A16
O
Address signal output terminal    Not used (open)
64 to 66
A15 to A13
O
Address signal output to the S-RAM (IC602)
67
GP10
O
L/R sampling clock signal (44.1 kHz) output to the D/A, A/D converter (IC605) and digital filter 
(IC606)
68
DECODE
O
Decode signal output to the system controller (IC501)
69
AUDIO
I
Bit 1 input terminal of channel status from the digital audio interface receiver (IC604)
70
VDDI
Power supply terminal (+2.6V)
71
VSS
Ground terminal
72 to 75
D15 to D12
I/O
Two-way data bus with the S-RAM (IC602)
76
VDDE
Power supply terminal (+3.3V)
77 to 80
D11 to D8
I/O
Two-way data bus with the S-RAM (IC602)
81
VSS
Ground terminal
82 to 85
A9, A12 to A10
O
Address signal output to the S-RAM (IC602)
86
TDO
O
Simple emulation data output terminal    Not used (open)
87
TMS
I
Simple emulation data input start/end detection signal input terminal    Not used (open)
88
XTRST
I
Simple emulation asychronous break input terminal    Not used (open)
89
TCK
I
Simple emulation clock signal input terminal    Not used (open)
90
TDI
I
Simple emulation data input terminal    Not used (open)
91
VSS
Ground terminal
92 to 97
A8 to A3
O
Address signal output to the S-RAM (IC602)
98, 99
D7, D6
I/O
Two-way data bus with the S-RAM (IC602)
100
VDDI
Power supply terminal (+2.6V)
101
VSS
Ground terminal
102 to 105
D5 to D2
I/O
Two-way data bus with the S-RAM (IC602)
106
VDDE
Power supply terminal (+3.3V)
107, 108
D1, D0
I/O
Two-way data bus with the S-RAM (IC602)
109, 110
A2, A1
O
Address signal output to the S-RAM (IC602)
111
VSS
Ground terminal
112
A0
O
Address signal output to the S-RAM (IC602)
113
PM
I
PLL reset signal input from the M61512FP (IC607)    “L”: reset
114, 115
SDI3, SDI4
I
Audio serial data input terminal    Not used (fixed at “L”)
116
SYNC
I
Synchronous/asychronous selection signal input terminal
“L”: Synchronous, “H”: asynchronous (fixed at “H” in this set)
117 to 119
VSS
Ground terminal
120
VDDI
Power supply terminal (+2.6V)
23
ST-S9
 DSP  BOARD  IC604  LC89056W-E (DIGITAL AUDIO INTERFACE RECEIVER)
Pin No.
Pin Name
I/O
Description
1
DISEL
I
Selection terminal of data input terminal    Fixed at “L” in this set
2
DOUT
O
Digital data output to the optical transceiver (IC609)
3
DIN0
I
Digital data input from the optical receiver (IC952) (for DVP-S9)
4
DIN1
I
Digital data input from the optical receiver (IC951) (for external input)
5
DIN2
I
Digital data input terminal    Not used (fixed at “L”)
6
DGND
Ground terminal (digital system)
7
DVDD
Power supply terminal (+3.3V) (digital system)
8
R
I
VCO gain control input terminal
9
VIN
I
VCO free run frequency setting input terminal
10
LPF
O
PLL loop filter setting output terminal
11
AVDD
Power supply terminal (+3.3V) (analog system)
12
AGND
Ground terminal (analog system)
13
CKOUT
O
Audio clock signal output to the CXD9617R (IC601)
14
BCK
O
Bit clock signal (2.8224 MHz) output to the CXD9617R (IC601)
15
LRCK
O
L/R sampling clock signal (44.1 kHz) output to the CXD9617R (IC601)
16
DATAO
O
Audio serial data output to the CXD9617R (IC601)
17
XSTATE
O
Source clock switching monitor output to the system controller (IC501)
18
DGND
Ground terminal (digital system)
19
DVDD
Power supply terminal (+3.3V) (digital system)
20
XMCK
O
Oscillation clock signal output to the CXD9617R (IC601)
21
XOUT
O
System clock output terminal (13.5 MHz)
22
XIN
I
System clock input terminal (13.5 MHz)
23
EMPHA
O
Emphasis information of channel status output terminal    Not used (open)
24
AUDIO
O
Bit 1 output terminal of channel status to the CXD9617R (IC601)
25
CSFLAG
O
Top 40 bit renovation flag output terminal of channel status    Not used (open)
26 to 28
F0 to F2
O
Input frequency calculation result output terminal    Not used (open)
29
VF
O
Validity flag output terminal    Not used (open)
30
DVDD
Power supply terminal (+3.3V) (digital system)
31
DGND
Ground terminal (digital system)
32
ERR9P
O
Nine times continuance data transmission error flag output terminal    Not used (open)
33
BPSYNC
O
Non-PCM burst and preamble sync signal output terminal    Not used (open)
34
ERROR
O
PLL lock error and data error flag output to the system controller (IC501)
35
DO
O
Read data output to the system controller (IC501)
36
DI
I
Write data input from the system controller (IC501)
37
CE
I
Chip enable signal input from the system controller (IC501)
38
CL
I
Clock signal input from the system controller (IC501)
39
XSEL
I
Selection input terminal of vibrator frequency terminal    Fixed at “H” in this set
40
MODE0
I
Mode setting input terminal    Fixed at “H” in this set
41
MODE1
I
Mode setting input terminal    Fixed at “H” in this set
42
DGND
Ground terminal (digital system)
43
DVDD
Power supply terminal (+3.3V) (digital system)
44
DOSEL0
I
Output data format selection signal input terminal    Fixed at “L” in this set
45
DOSEL1
I
Output data format selection signal input terminal    Fixed at “L” in this set
46
CKSEL0
I
Output clock selection signal input terminal    Fixed at “L” in this set
47
CKSEL1
I
Output clock selection signal input terminal    Fixed at “L” in this set
48
XMODE
I
System reset signal input from the M61512FP (IC607)
24
ST-S9
 DSP  BOARD  IC605  AK4527 (A/D, D/A CONVERTER)
Pin No.
Pin Name
I/O
Description
1
SDOS
I
Audio serial data source selection signal input terminal
“L”: internal ADC output, “H”: DAUX input (fixed at “L” in this set)                                               
2
I2C
I
Serial control mode selection signal input terminal    “L”: 3-wire serial, “H”: I2C bus                      
3
SMUTE
I
Soft muting on/off signal input from the system controller (IC501)    “L”: muting on
4
BICK
I
Bit clock signal (2.8224 MHz) input from the CXD9617R (IC601)
5
LRCK
I
L/R sampling clock (44.1 kHz) signal input from the CXD9617R (IC601)
6 to 8
SDTI1 to SDIT3
I
Audio serial data input from the CXD9617R (IC601)
9
SDTO
O
Audio serial data output to the CXD9617R (IC601)
10
DAUX
I
Audio serial data input terminal    Not used (fixed at “L”)
11
DFS
I
Double speed sampling mode signal input terminal
“L”: normal speed, “H”: double speed (fixed at “L” in this set)
12
DEM1
I
De-emphasis signal input terminal    Fixed at “L” in this set
13
DEM0
I
De-emphasis signal input terminal    Fixed at “H” in this set
14
TVDD
Power supply terminal (+5V) (for output buffer )
15
DVDD
Power supply terminal (+5V) (digital system)
16
DVSS
Ground terminal (digital system)
17
PDN
I
Power down and reset signal input from the M61512FP (IC607)    “L”: power down and reset
18 to 20
ICKS2 to ICKS0
I
Input clock signal selection terminal    Fixed at “L” in this set
21, 22
CAD1, CAD0
I
Chip address signal input terminal    Not used (fixed at “L”)
23
LOUT3
O
Analog signal output for center to the M61512FP (IC607)
24
ROUT3
O
Analog signal output for sub woofer to the M61512FP (IC607)
25
LOUT2
O
Analog signal output for surround L-ch to the M61512FP (IC607)
26
ROUT2
O
Analog signal output for surround R-ch to the M61512FP (IC607)
27
LOUT1
O
Analog signal output for front L-ch to the M61512FP (IC607)
28
ROUT1
O
Analog signal output for front R-ch to the M61512FP (IC607)
29
LIN–
I
L-ch analog signal negative input from the M61512FP (IC607)
30
LIN+
I
L-ch analog signal positive input from the M61512FP (IC607)
31
RIN–
I
R-ch analog signal negative input from the M61512FP (IC607)
32
RIN+
I
R-ch analog signal positive input from the M61512FP (IC607)
33
DZF2
I
Zero input detection terminal     Not used (open)
34
VCOM
O
Common voltage output terminal                                                                                                         
Large external capacitor is used to reduce power supply noise
35
VREFH
I
Reference voltage (+5V) input terminal
36
AVDD
Power supply terminal (+5V) (analog system)
37
AVSS
Ground terminal (analog system)
38
DZF1
I
Zero input detection terminal     Not used (open)
39
MCLK
I
Master clock signal input from the CXD9617R (IC601)
40
P/S
I
Parallel/serial selection signal input terminal
“L”: serial control mode, “H”: parallel control mode (fixed at “H” in this set)
41
DIF0
I
Audio data interface format terminal    Fixed at “L” in this set
42
DIF1
I
Audio data interface format terminal    Fixed at “H” in this set
43, 44
LOOP0, LOOP1
I
Loop back mode setting terminal    Fixed at “L” in this set
25
ST-S9
 PANEL BOARD  IC601  MB90M407PF-G-109-BND (DISPLAY CONTROLLER)
Pin No.
Pin Name
I/O
Description
1 to 6
G6 to G1
O
Grid drive signal output to the fluorescent indicator tube (FL601)
7 to 10
A1 to A4
O
Segment drive signal output to the fluorescent indicator tube (FL601)
11
VSS FOR IO
Ground terminal (for I/O)
12 to 22
A5 to A15
O
Segment drive signal output to the fluorescent indicator tube (FL601)
23
VDD FOR VFT
Power supply terminal (+3.3V) (for VFT)
24 to 41
A16 to A33
O
Segment drive signal output to the fluorescent indicator tube (FL601)
42
VSS FOR IO
Ground terminal (for I/O)
43 to 47
A34 toA38
O
Segment drive signal output to the fluorescent indicator tube (FL601)
48
VKK FOR VFT
Power supply terminal (–28V) (for VFT)
49
MODE0
Chip mode selection terminal     Not used (fixed at  “H”)
50
MODE1
Chip mode selection terminal     Not used (fixed at  “H”)
51
MODE2
Chip mode selection terminal     Not used (fixed at  “L”)
52
JOG2B
I
Jog dial pulse input from the rotary encoder (for sound) in the TA-S9D (B phase input)
53
JOG2A
I
Jog dial pulse input from the rotary encoder (for sound) in the TA-S9D (A phase input)
54
JOG1B
I
Jog dial pulse input from the rotary encoder (for function) in the TA-S9D (B phase input)
55
JOG1A
I
Jog dial pulse input from the rotary encoder (for function) in the TA-S9D (A phase input)
56
VOLA
I
Jog dial pulse input from the rotary encoder (for volume) in the TA-S9D (A phase input)
57
VOLB
I
Jog dial pulse input from the rotary encoder (for volume) in the TA-S9D (B phase input)
58, 59
Not used (open)
60
I2C DATA
I/O
Communication data bus with the system controller (IC501) and DVP-S9
61
I2C CLK
I/O
Communication data reading clock signal input or transfer clock signal output with the system 
controller (IC501) and DVP-S9
62
AVCC FOR 
ANALOG
Power supply terminal (+3.3V) (for analog)
63
AVSS FOR 
ANALOG
Ground terminal (for analog)
64
KEY0
I
Key input terminal (A/D input)    CLOCK/TIMER, TIMER SELECT, TUNER/BAND, TUNING 
+/–, ENTER,  PRESET +/–, TUNER MEMORY, STEREO/MONO, PTY (S602 to S612) keys 
input    PTY (S612) key: Used for the AEP and UK models
65
KEY1
I
Key input terminal for TA-S9D (A/D input)
66 to 76
Not used (open)
77
RESET
I
Reset signal input from the system controller (IC501)    “L”: reset
78 to 80
Not used (open)
81
VSS FOR CPU
Ground terminal (for CPU)
82
XIN
I
System clock input terminal (4 MHz)
83
XOUT
O
System clock output terminal (4 MHz)
84
VCC FOR CPU
Power supply terminal (+3.3V)
85 to 91
Not used (open)
92 to 94
G12
O
Grid drive signal output to the fluorescent indicator tube (FL601)
95 to 98
G11 to G8
O
Grid drive signal output to the fluorescent indicator tube (FL601)
99, 100
G7
O
Grid drive signal output to the fluorescent indicator tube (FL601)
26
ST-S9
6-1. CASE,  FRONT  PANEL  SECTION
SECTION  6
EXPLODED  VIEWS
• Items marked “*” are not stocked since they
are seldom required for routine service. Some
delay should be anticipated when ordering
these items.
• The mechanical parts with no reference num-
ber in the exploded views are not supplied.
NOTE:
• -XX and -X mean standardized parts, so they
may have some difference from the original
one.
• Color Indication of Appearance Parts
Example:
KNOB, BALANCE (WHITE) . . . (RED)
Parts Color Cabinet's Color
• Abbreviation
AUS
: Australian model
EA
: Saudi Arabia model
KR
: Korean model
MX
: Mexican model
SP
: Singapore model
TH
: Thai model
#1
#2
2
3
4
5
6
5
AEP, UK
5
7
8
7
1
Ref. No.
Part No.
Description
Remark
Ref. No.
Part No.
Description
Remark
1
X-4953-451-1 PANEL ASSY (ST), FRONT (AEP, UK)
1
X-4953-452-1 PANEL ASSY (ST), FRONT
(AUS, EA, E, KR, MX, SP, TH)
2
1-773-114-11 WIRE (FLAT TYPE) (19 CORE)
3
4-232-351-01 FILTER (FL)
4
1-680-697-11 SIRCS BOARD
5
4-951-620-01 SCREW (2.6X8), +BVTP
6
A-4727-699-A PANEL BOARD, COMPLETE (AEP, UK)
6
A-4727-701-A PANEL BOARD, COMPLETE (TH)
6
A-4727-702-A PANEL BOARD, COMPLETE
(AUS, EA, E, KR, MX, SP)
7
3-363-099-21 SCREW (CASE 3 TP2)
8
4-233-134-31 CASE
#1
7-685-646-79 SCREW +BVTP (3X8 TYPE2 N-S)
#2
7-685-871-01 SCREW +BVTT (3X6 (S))

Click on the first or last page to see other MHC-S9D / ST-S9 service manuals if exist.