Read Sony HCD-VX222 / MHC-VX222 Service Manual online
46
HCD-VX222
VIDEO BOARD IC502 M30620MCA-B22FP (CD MECHANISM CONTROLLER)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42, 43
44
45
46
47
48
49
50
51
I/O
I
O
O
O
O
O
I
I
—
O
O
I
O
—
I
I
I
I
O
I
O
O
I
O
I
O
O
O
I/O
I/O
O
I
O
O
O
I
O
O
I
O
I
O
I
I
O
O
O
O
O
I
Description
Internal status (SENSE) signal input from the CXD3008Q (IC101)
Sense serial data reading clock signal output to the CXD3008Q (IC101)
Y resolution output
Chroma level output
Serial data transfer clock signal output to the CXD3008Q (IC101)
Not used (open)
Remote control signal input terminal. Not used (open)
External data bus line byte selection signal input “L”: 16 bit, “H”: 8 bit (fixed at “L”)
Ground terminal
Muting on/off control signal output to the CXD3008Q (IC101) “H”: muting on
Clock selection signal output to the CXD3008Q (IC101) “L”: 16.9344 MHz (double speed), “H”: 33.8688 MHz
Reset signal input from the system controller (IC501) “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
Main system clock output terminal (10 MHz)
Ground terminal
Main system clock input terminal (10 MHz)
Power supply terminal (+5V)
Non-maskable interrupt input terminal (fixed at “H” in this set)
Subcode sync (S0+S1) detection signal input from the CXD3008Q (IC101)
Not used (open)
Interrupt request signal input from the host MPU (IC505)
Video CD select data of the host MPU (IC505)
Serial data latch pulse output to the D/A converter (IC509) “L” active
Ready signal input for communication to the host MPU (IC505)
Reset signal output to the MPEG video/audio decoder (IC505) “L”: reset
Horizontal sync signal input
Burst gate pulse signal output
AGC hold signal output
Laser power selection signal output to the CXA2568M (IC103) “H”: laser on
I
2
C clock signal from CD mechanism control (IC501).
I
2
C data signal from CD mechanism control (IC501).
Serial data output to the MPEG video/audio decoder (IC506) and D/A converter (IC509)
Serial data input from the MPEG video/audio decoder (IC506)
Serial data transfer clock signal output to the MPEG video/audio decoder (IC506) and D/A converter (IC509)
RTS signal to serial port (check connector).
Not used (open)
Sub-code Q data input from the CXD3008Q (IC101)
Sub-code Q data reading clock signal output to the CXD3008Q (IC101)
Power on/off control signal output terminal. Not used (open)
Ready signal input terminal. Not used (fixed at “H”)
Not used (open)
Hold signal input terminal. Not used (fixed at “H”)
Not used (open)
OSD language select input terminal “H”: English, “L”: China
Vertical sync signal input
Bus write signal output.
Not used (open)
Audio muting on/off control signal output terminal “L”: muting on. Not used (open)
Loading motor drive signal output terminal. Not used (open)
Loading motor drive signal output terminal. Not used (open)
Disc detection (load in) switch input terminal. Not used (fixed at “H”)
Pin Name
SENSE
SENSE CLK
RESOLUTION
CHROMA LEVEL
DSP CLK
TSENS
REMOTE IN
BYTE
CN VSS
DSP MUTE
CTRL1
XRESET
XOUT
VSS
XIN
VCC
NMI
SCOR
DSENS
CL680 HINT
CL680 HSEL
DF LATCH
CL680 HRDY
CL680 RESET
H.SYNC IN
BGP
LPH
LD ON
12C.CLK
12C.DATA
DATA1O
DATA1I
CLK1
RTS1
XVLEVEL.DOWN
SUBQ DATA
SUBQ CLK
P.ON
BUS XRDY
BUS
BUS XHOLD
BUS
OSD.LANGUAGE
VSYNC
BUS XWRL
LO.BOOST
AUDIO MUTE
LOAD OUT
LOAD IN
INSW
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