Read Sony HCD-RV660D / HCD-RV990D Service Manual online
28
HCD-RV660D/RV990D
Pin No.
Pin Name
I/O
Pin Description
151
DATA1(FLR)
O
Audio data (front L/R signal) output to 2CH DAC IC (HCD-RV660D) and D/A
converter IC (HCD-RV990D).
152
VDDP
—
Power supply pin (+3.2 V) (I/O signal)
153
GNDP
—
Ground (I/O signal)
154
DATA2(SLR)
O
Audio data (rear L/R signal) output to D/A converter IC (HCD-RV990D).
155
DATA3(CSW)
O
Audio data (center/subwoofer signal) output to D/A converter IC (HCD-RV990D).
156
IEC958
O
S/PDIF signal output
157
DAI_DATA
I
Not used (Open)
158
DAI_BCK
I
Not used (Open)
159
DAI_LRCK
I
Not used (Open)
160
I2C_CL
I/O
I2C clock bus signal input from/output to mechanism control IC.
161
I2C_DA
I/O
I2C data bus signal input from/output to mechanism control IC.
162
CS(ZIVA_E2P)
O
Chip select signal output to EEPROM IC.
163
RXD1
I
Serial data input from check jig
164
TXD1
O
Serial data output to check jig
165
WRITE_CTRL(ZIVA_E2P)
O
Write control signal output to EEPROM IC.
166
GNDP
—
Ground (I/O signal)
167
VDDP
—
Power supply pin (+3.2 V) (I/O signal)
168 to 171
SDDATA7 to SDDATA4
I
SDBUS data input from DVD decoder IC.
172
GND
—
Ground (inside core)
173
VDD
—
Power supply pin (+1.8 V) (inside core)
174 to 177
SDDATA3 to SDDATA0
I
SDBUS data input from DVD decoder IC.
178
SDREQ
O
SDBUS data request signal output to DVD decoder IC.
179
SDEN
I
SDBUS data enable signal input from DVD decoder IC.
180
GNDP
—
Ground (I/O signal)
181
VDDP
—
Power supply pin (+3.2 V) (I/O signal)
182
SDERROR
I
SDBUS data error signal input from DVD decoder IC.
183
SDCLK
I
SDBUS data clock signal input from DVD decoder IC.
184
HIRQ1
I
Interrupt signal input from mechanism control IC.
185
DRVCLK
I
Serial data clock signal input from mechanism control IC.
186
DRVTX
I
Serial data input from mechanism control IC and EEPROM IC.
187
DRVRX
O
Serial data output to mechanism control IC and EEPROM IC.
188
DRVRDY
I
Ready signal input from mechanism control IC.
189
VNW
—
Power supply for 5 V tolerance voltage input
190
ALE
O
Latch enable signal output for address data demux.
191
RST_SPC
O
Reset signal output to mechanism control IC.
192
INT/EXT
O
Not used (Open)
193
HCS2
O
Not used (Open)
194
HCS1
I/O
Not used (Open)
195
HCS0
O
Chip select signal output to programmable ROM IC.
196
VDDP
—
Power supply pin (+3.2 V) (I/O signal)
197
TRST
I
Reset signal input
198
TDO
O
Data output
199
TDI
I
Data input
200
TMS
I
TMS signal input
201
TCK
I
TCK signal input
202
RESET
I
ZIVA reset signal input
203
BUS CLK
I/O
Not used (Open)
204
GND
—
Ground (inside core)
205
VDD
—
Power supply pin (+1.8 V) (inside core)
206, 207
HA3, HA2
I/O
Address bus signal input from/output to bus interface IC.
208
GNDP
—
Ground (I/O signal)
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