Read Sony HCD-DP1000D Service Manual online
HCD-DP1000D
54
54
6-33. IC PIN FUNCTION DESCRIPTION
Description
Pin Name
Pin No.
I/O
• IC103 MB91307APFV-G-BND-E1 DVD SYSTEM CONTROL (MB BOARD (4/5))
Description
Pin Name
Pin No.
I/O
1
HA17
O
Address bus to SRAM
2
HA18
O
Address bus to SRAM
3
HA19
O
Address bus to SRAM
4
HA20
O
Address bus to SRAM
5
HA21
O
Address bus to SRAM
6
HA22
O
Address bus to SRAM (Not used)
7
WP
O
Chip select signal output to EEPROM
8
TRM/XKRCS
O
Not used (open)
9
AVCC
I
Power supply +3.3V
10
AVRH
I
A/D reference voltage input (Connected to AVCC)
11
AVSS
—
Ground
12
AN0
I
A/D input pin (mode set)
13
AN1
I
A/D input pin (mode set)
14
AN2
I
A/D input pin (mode set)
15
AN3
I
A/D input pin (mode set)
16
INT0
I
HIREQO signal input from CXD1933Q
17
INT1
I
XINT signal input from CXD9635R
18
INT2
I
HINT signal input from CXD9635R
19
INT3
I
FGAINT signal input from LC22004A
20
INT4
I
XIFINT signal input from M30622MGA
21
INT5
I
Not used (open)
22
INT6
I
Not used (open)
23
INT7
I
Not used (open)
24
VCC
I
Power supply +3.3V
25
SI0
I
Serial data input from M30622MGA
26
SO0
O
Serial data output to M30622MGA
27
SC0
O
Clock output to M30622MGA
28
SI1
I
Not used (open)
29
SO1
O
Not used (open)
30
SC1
O
Not used (open)
31
SI2
I
Test serial data input
32
SO2
O
Test serial data output
33
DSENS
O
Not used (open)
34
VSS
—
Ground
35
XRST
O
Reset signal output
36
XARPRST
O
XARP reset signal output to CXD9635R
37
RGBSEL/MICMUTE
O
Not used (open)
38
SDA
I/O
Serial data input/output to EEPROM
39
SCL
O
Serial clock output to EEPROM
40
TRM+XKRRST
O
Not used (open)
41
EUROV/V/CLAPSW1
O
Not used (open)
42
DISCEXT/CLPSW0
O
Not used (open)
43
MD0
I
Mode signal input (connected to VCC)
44
MD1
I
Mode signal input (connected to VSS)
45
MD2
I
Mode signal input (connected to VSS)
46
DREQ0
I
DMA external transfer request input
47
DACK0
O
DMA external transfer request acknowledge output
48
XDRVMUTE
O
Mute signal output to FAN8034
49
DREQ1
I
DMA external transfer request input
50
DACK1
O
DMA external transfer request acknowledge output
51
XIFCS
O
XIFCS signal output to M30622MGA
52
VSS
—
Ground
53
X1
I
External crystal terminal (16.5MHz)
54
X0
O
External crystal terminal (16.5MHz)
55
VCC
I
Power supply +3.3V
56
CKSW1
I
Not used (connected toVCC)
57
OCSW1
I
Not used (connected toVCC)
58
CS0X
O
Chip select signal output to FLASH RAM
59
CS1X
O
Not used (open)
60
CS2X
O
AVDCS2 signal output to CXD1933Q
61
CS3X
O
AVDCS3 signal output to CXD1933Q
62
CS4X
O
XARPCS signal output to CXD1933Q
63
CS5X
O
XSPDCS signal output to CXD1933Q
64
C
—
External capacitor terminal
65
CS6X
O
XFAGCS signal output to CXD1933Q
66
CS7X
O
Not used (open)
67
XWAIT
I
XWAIT signal input from CXD1933Q
68
BGRNTX
I
Not used (connected toVCC)
69
BGR
O
Not used (open)
70
XRD
O
Out enable signal output to FLASH RAM
71
XWRH
O
Write signal output to FLASH RAM
72
XWRL
O
Not used (open)
73
XMIX
I
Not used (connected toVCC)
74
HSTX
I
Not used (connected toVCC)
75
VSS
—
Ground
76
XFRRST
I
System reset input from M30622MGA
77
CPUCK
O
Clock signal output to LC22004A
78
OCSW2
I
Not used (connected toVCC)
79
XBACK
I
Not used (connected toVCC)
80
VESCS/X39CS
I
Not used (connected toVCC)
81
48/44.1K
O
Audio clock control signal output
82
WIDE
O
WIDE control signal output
83
MAMUTE
I
System OK signal input to M30622MGA
84
XLDON
O
Laser diode ON signal output
85
HD0
I/O
Data input/output to SRAM
86
HD1
I/O
Data input/output to SRAM
87
HD2
I/O
Data input/output to SRAM
88
HD3
I/O
Data input/output to SRAM
89
HD4
I/O
Data input/output to SRAM
90
HD5
I/O
Data iniput/output to SRAM
91
HD6
I/O
Data input/output to SRAM
92
HD7
I/O
Data input/output to SRAM
93
HD8
I/O
Data input/output to SRAM
94
HD9
I/O
Data input/output to SRAM
95
HD10
I/O
Data input/output to SRAM
96
HD11
I/O
Data input/output to SRAM
97
HD12
I/O
Data input/output to SRAM
98
HD13
I/O
Data input/output to SRAM
99
HD14
I/O
Data input/output to SRAM
100
HD15
I/O
Data input/output to SRAM
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