Read Sony DHC-MD7 / MDS-M9 Service Manual online
— 57 —
I/O
Function
Pin No.
Pin Name
48, 49
50
51
52 to 55
56 to 60
61
62
63
64
65
66
67
68, 69
70, 71
72 to 74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
A11, A10
VSS
VDD
A03 to A00
A04 to A08
XOE
XCAS
VSS
XCS
A09
XRAS
XWE
D1, D0
D2, D3
D4 to D6
VSS
D7
ERR
EXTC2R
BUSY
EMP
FUL
EQL
MDLK
CPSY
CTMD0
CTMD1
SPO
VSS
MDSY
LRCK
BCK
C2PO
DATA
DIDT
DODT
DIRCPB
MIN
SPOSL
MCK
VSS
O
—
—
O
O
O
O
—
O
O
O
O
I/O
I/O
I/O
—
I/O
I/O
I
O
O
O
O
O
O
O
O
O
—
O
I
I
I
I/O
I
O
O
I
I
O
—
Address signal output. Not used in this unit (Opened)
Ground pin
Power supply pin (+5V)
Output of address signal to RAM (IC272)
Output of output enable control signal to RAM (IC272)
Output of column address strobe signal to RAM (IC272)
Ground pin
Output of chip select signal to RAM (IC272). Not used in this unit (Opened)
Output of address signal to RAM (IC272)
Output of row address strobe signal to RAM (IC272)
Output of read/write control signal to RAM (IC272)
Input/output pin of data signal to/from RAM (IC272)
Data signal input/output pin. Not used in this unit (Opened)
Ground pin
Data signal input/output pin. Not used in this unit (Opened)
Input/output pin of error (C2PO) data to external RAM. Not used in this unit (Opened)
External RAM selection input for error data writing (“H”: External RAM). (Fixed at “L”)
RAM access BUSY signal output. Not used in this unit (Opened)
EMPTY or immediately before FULL of ATRAC data (When DSC=ASC+1: “H”).
Not used in this unit (Opened)
FULL or immediately before EMPTY of ATRAC data (When ASC=DSC+1: “H”).
Not used in this unit (Opened)
ATRAC data EMPTY (When DSC=ASC: “H”). Not used in this unit
Indicates recording/playback data main/sub (“H”: Sub, Linking: “L”: Main). Not used in
this unit
Interpolation sync signal output. Not used in this unit
DSC counter mode output. Not used in this unit
Output of system clock (512fs=22.5792 MHz) signal to CXD2535BR (IC121)
Ground pin
Main data sync detection signal output. Not used in this unit
Input of L/R clock signal from CXD2535BR (IC121) (44.1 kHz)
Input of bit clock signal from CXD2535BR (IC121) (2.8224 MHz)
Input of C2PO signal from CXD2535BR (IC121) (Shows data error status)
Playback:C2PO (“H”). Digital recording: D.In-Vflag. Analog recording: “L”
Recording:Output of recording audio data signal to CXD2535BR (IC121)
Playback:Input of playback audio data signal from CXD2535BR (IC121)
Input of digital audio input 16-bit data from CXD2535BR (IC121)
Output of digital audio output 16-bit data to CXD2535BR (IC121)
Disc drive and EFM encoder/decoder recording/playback mode output. Not used in this unit
Input of defect ON/OFF switching signal from CXD2535BR (IC121)
Pin 87 (SPO) input/output switching input pin (“L”:IN. “H”:OUT). (Fixed at “H”)
RAM controller internal master clock output pin. Not used in this unit
Ground pin
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