DHC-MD555 (serv.man2) - Sony Audio Service Manual (repair manual). Page 6

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The following describes the terminals of CONTROL I.

SDA (I2C serial data):1 pin
SCL (I2C serial clock):5 pin

In the communication between microprocessors inside the current system stereo, the DATA line is expanded to four lines based on the AU

BUS, and a 6-line Y BUS with additional CLK and BUSY lines is used as the internal bus. System stereos after DHC-MD555, DHC-MD777,
and JMD-7 however adopt the Phillips “I2C format” for the communication format of the internal bus.

The I2C format bus is able to send a higher volume of data than the conventional Y-BUS using two lines serial data (SDA) and serial

clocks (SCL) and at high speed. By performing this I2C bus using the system stereo terminal, high speed communication between the system
stereo internal microprocessor and microprocessor of external equipments is possible.

The microprocessor incorporated in the CAV-PX1 connection cable of the PC connection kit PCLK-PX1 and microprocessor incorpo-

rated in the transmitter receiver of the bi-directional remote control RM-IA10K communicate with the microprocessor of the system stereo
via the CONTROL I terminal.

The microprocessor of the optional cassette deck TC-PX100 and TC-SD1 communicates with the system stereo microprocessor via a

exclusive connector.

When the I2C bus inside the system stereo is connected to an external equipment using a connection cable, rounding of waveform occurs

from the effects of the stray capacitance of the cable. When the cable is longer and the stray capacitance increases, the rounding of the
waveform increases, and may disable communication of the I2C bus.

For this reason, I2C dedicated buffer ICs are used for both the system stereo and external equipment to prevent I2C bus effects even when

the cable is connected.

When the power of the system stereo is in the STAND BY state, all functions are stopped except for some microprocessor functions in

order to decrease the power consumption. In this sleep mode, no communication operations by the I2C bus communication terminals SDA
and SCL are possible.

In the sleep mode, as the power of the I2C buffer IC is also turned off, the internal I2C bus and buffer ICs are cut off by the MOS-FET

switch to prevent incorrect operations by the effects of the external equipment.

VDD:4 pin

+5V is supplied from the system stereo only when the system stereo is in the power ON state. No power will be supplied in the STAND

BY state.

The I2C buffer IC in the system stereo and I2C buffer IC of the external equipment operate with this power. It prevents from that the

communication becomes impossible after one power is turned off.

The connection cable CAV-PX1 of the PCLK-PX1 incorporates the internal I2C buffer IC, 12C-RS232C conversion microprocessor, and

RS232C driver IC. These IC powers are all supplied at +5V from the system stereo.

The main power supply of the RM-IA10K transmitter receiver is supplied by the AC adapter. Only the power of the I2C buffer IC is

supplied from the system stereo. Although the optional TC also has its own power supply, only the power of the I2C buffer IC is supplied
from the system stereo.

When the power of the system stereo is ON, if the power of the above external equipment is OFF, power is supplied from the system stereo

to the I2C buffer IC in the external equipment. But, this power is cut by the MOS-FET SW between the I2C buffer IC and the microprocessors
of external equipment, and therefore has no effect on the I2C bus of the system stereo.

The power of the connection CAV-50C of the MDS-PC1 and PCLK-MD1 using the CONTROL-A1 terminal is created from the RS232C

signal of the PC and is not supplied from the component stereo.