DAV-S500, DAV-S800, HCD-S800 - Sony Audio Service Manual (repair manual). Page 61

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61
HCD-S500/S800
Pin No.
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85 to 100
101
102 to 109
110
111 to 118
119
120
I/O
I
I
O
O
O
O
O
O
I
I
I
O
O
O
I
O
I
O
O
I
O
I/O
O
O
O
Pin Name
VCC
CKSW1
OCSW1
CS0X
CS1X
CS2X
CS3X
CS4X
CS5X
C
CS6X
CS7X
XWAIT
BGRNTX
BRQ
XRD
XWRH
XWRL
XMIX
HSTX
VSS
XFRRST
CPUCK
OCSW2
XDACK
VESCS/X39CS
48/44.1K
WIDE
MAMUTE
XLDON
HD0 -15
VSS
HA0 - 7
VCC
HA8 - 15
VSS
HA16
Description
Power supply
Chucking switch (Tray SW1) signal input
Open/Close switch (Tray SW2) signal input
Chip select signal output to external ROM
Not used
Chip select signal output to AVD SDRAM
Chip select signal output to AVD R-BUS
Chip select signal output to IC302(CXD8635R/ARP)
Chip select signal output to IC302(CXD8635R/SDSP)
Terminal for built-in regulator bypass capacitor
FGA CS output
Not used
external WAIT signal input
External bus open aclnowledge signal input (pull-up)
External bus open request signal input
External bus read enable signal output
Write signal output for upper byte
Write signal output for lower byte
Not used
Not used (pull-up)
Ground
Reset signal input
CPU clock output
Tray switch signal input
Not used (pull-up)
Not used (pull-up)
PLL IC control signal output
Video wide offset control signal output
IFOK signal input from IC901(CPU)
Laser diode mute control signal output
External data bus bits 0 - 15
Ground
Address signal output
Power supply
Address signal output
Ground
Address signal output
62
HCD-S500/S800
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
O
O
I
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Description
Digital Ground
CPU data
Digital power supply 3.3V
CPU address
Digital Ground
CPU address
Digital power supply 1.8V
Interrupt
Host interrupt(DSP)
Tip select
Host servo tip select
Wait
Digital Ground
DRAM address
Digital power supply 3.3V
DRAM write enable
DRAM CAS
Digital Ground
DRAM RAS
DRAM output enable
Digital power supply 1.8V
DRAM data
Pin Name
VSS
D0
D1
D2
D3
D4
D5
D6
D7
VDD 3.3V
A0
A1
A2
A3
A4
VDD
A5
A6
A7
VDD 1.8V
XINT
HINT
XCS
HCS
XWAT
VSS
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
VDD 3.3V
XMWR
XCAS
VSS
XRAS
XOE
VDD1 1.8V
MD0
MD1
MD2
MD3
MD4
MD5
MD6
• IC302
 CXD9635R (SERVO DSP) (DVD BOARD)
63
HCD-S500/S800
Pin No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
I/O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I/O
O
O
O
O
O
O
Description
DRAM data
Digital Ground
DRAM data
Digital power supply 3.3V
CDDA data
CDDA bit clock
Digital Ground
CDDA LR clock
Digital out
Digital power supply 1.8V
SD bus clock
SD bus header
SD bus REQ
SD bus ACK
SD bus error flag
SD bus data
Digital Ground
SD bus data
Digital power supply 3.3V
Monitor bus
Error storbe
Digital power supply 1.8V
RF digital data in/out
Digital Ground
PLCK output
ADC output
Pin Name
MD7
VSS
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
VDD 3.3V
DATA
BCLK
VSS
LRCK
DOUT
VDD 1.8V
SDCK
XSHD
XSRQ
XSAK
SDEF
SD0
SD1
SD2
SD3
VSS
SD4
SD5
SD6
SD7
VDD 3.3V
MNT0
MNT1
MNT2
MNT3
MNT4
MNT5
MNT6
MNT7
ESTB
VDD 1.8V
RFD
VSS
PLCKO
ADO0
ADO1
ADO2
ADO3
ADO4
64
HCD-S500/S800
Pin No.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
I/O
O
O
O
I
I
I
I
I
I
I
I
O
I
I
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
Description
ADC output
Digital Ground
Analog Ground
VCO control input
VCO outside resistance 1
VCO outside resistance 2
Analog power supply
Analog Ground
OP amp positive input
OP amp negative input
Feedback resistance 3
Feedback resistance 2
Feedback resistance 1
OP amp output
Analog power supply
DAC reference voltage
DAC bias pin
Analog power supply
Analog Ground
DAC output
Reference current of DAC
Digital Ground(DAC)
Digital power supply(DAC)
ADC reference
Analog power supply
RF input
RF input
Analog Ground
RF input
ADC reference
Digital Ground(ADC)
Digital power supply(ADC)
ADC input
ASW analog power supply
ADC input
ASW analog ground
ADC input
ADC digital power supply(DSP)
ADC digital ground DSP
ADC reference
Analog ground(ADC)
ASW output
ADC analog power supply(DSP)
Pin Name
ADO5
ADO6
ADO7
VSS
VSSA4
VCO
R1
R2
VDDA4 3.3V
VSSA3
INP
INM
FR3
FR2
FR1
Y
VDDA3 3.3V
VREF
BIAS
VDDA2 3.3V
VSSA2
AOUT
IREF
VSSD2
VDDD2 3.3V
VRT
VDDA1 3.3V
RFIN1
AIN
VSSA1
RFIN1
VRB
VSSD1
VDDD1 3.3V
ADC0
ADC1
ADC2
VDDA0 3.3V
ADC3
ADC4
VSSA0
ADC5
ADC6
ADC7
VDDD0 3.3V
VSSD0
VRBA
VSSA0
TESTAA
VDDA0 3.3V
65
HCD-S500/S800
Pin No.
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
I/O
I
I
I
I
I
I
O
O
O
I/O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
O
I
I
O
O
O
Description
ADC reference
Digital Ground
Test terminal L
DSP reset
Reset
Digital Ground
CLV speed error
Motor on
CLV phase error
Defect detection output
Jitter PWM output
EFM lock detection
Digital power supply 1.8V
GIO/external interruption
Digital power supply 3.3V
GIO/PGREF input
GIO/PGIN input
GIO/serial data in
GIO/serial data out
GIO/serial clock
GIO/FGREF input
GIO/FGIN input
GIO/Timer 2 clock input
GIO(input and output)
Digital Ground
Clock input
Analog Ground
Analog power supply
Defect input
Digital Ground
Clock for ECC 33MHz
Digital power supply 1.8V
System clock
Digital Ground
JTAG Boundary scan
TZC input
MIRR input
PWM output
Pin Name
VRTA
VSS
TESTK0
TESTK1
TESTK2
XDSPRST
XARPRST
VSS
MDS0
MON
MDP0
DFCT
JITPWM
LOCK
VDD1 1.8V
GIO0/INT2
GIO1/INT3
GIO2/INT4
GIO3/INT5
VDD 3.3V
GIO4/PGREF
GIO5/PGIN
GIO6/SDI
GIO7/SDO
GIO8/SCK
GIO9/FGREF
GIO10/FGIN
GIO11/TMC2
GIO12
GIO13
VSS
CLKIN
VSSA5
VDDA5 1.8V
DFCTI
VSS
MCKI
VDD 1.8V
SCKI
VSS
TRST
TMS
TDI
TCK
TDO
TZC
MIRR
PWM0
PWM1
PWM2
66
HCD-S500/S800
Pin No.
201
202
203
204
205
206
207
208
I/O
O
O
O
O
I
I
Description
Digital power supply 3.3V
PDM output
Digital Ground
CPU light
CPU lead
Pin Name
VDD 3.3V
PDM0
PDM1
PDM2
PDM3
VSS
XWR
XRD
67
HCD-S500/S800
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18 to 25
26
27
28
29
30
31
32 to 34
35
36
37
38 to 41
42
43, 44
45
46, 47
48
49
50
51, 52
53
54
55, 56
57
58
59
60
61
62
63
64
65
66
I/O
I
I
I
O
O
O
I
I
I
O
O
O
O
O
I
I
O
I
I
I
O
O
O
O
O
O
O
I
O
O
I
I
O
I
O
O
O
O
O
Pin Name
VSCA0
XMSLAT
MSCK
MSDATI
VDCA0
MSDATO
MSREADY
XMSDOE
XRST
SMUTE
MCKI
VSIOA0
EXCKO1
EXCKO2
LRCK
F75HZ
VDIOA0
MNT0 - 7
TCK
TDI
VSCA1
TDO
TMS
TRST
TEST1 - 3
VDCA1
UBIT
XBIT
SUPDT0 - 3
VSIOA1
SUPDT4 - 5
VDIOA1
SUPDT6 - 7
SUPEN
VSCA2
NC
TEST4 - 5
NC
VDCA2
NC
BCKASL
VXDSD0
BCKAI
BCKAO
PHREFI
PHREFO
ZDFL
DSAL
ZDFR
DSAR
Description
Ground
Latch signal input for micom serial communication
Shift clock input for micom serial communication
Data input for micom serial communication
Power supply
Data output for micom serial communication
Output ready flag output for micom serial communication
Output enable signal output for micom serial communication
Reset signal input
Soft mute signal input (H:soft mute, L:off)
Master clock input (768Fs 33.8688MHz)
Ground for I/O
External clock output 1
External clock output 2 (not used)
Clock output (1Fs 44.1kHz)(not used)
Frame signal output
Power supply for I/O
Monitor signal output (not used)
Test clock input (connected to ground)
Input terminal for test
Ground
Output terminal for test (open)
Input terminal for test (open)
Reset terminal for test (open)
Input terminal for test (connected to ground)
Power supply
Output terminal for test (open)
DST monitor terminal (open)
Supplementary data output (open)
Ground for I/O
Supplementary data output (open)
Power supply for I/O
Supplementary data output (open)
Supplementary data acknoledge output (open)
Ground
Output terminal for test (open)
Input terminal for test (connected to ground)
Output terminal for test (open)
Power supply
Output terminal for test (open)
Bit clock I/O selection signal input for DSD data output (L:slave, H:master)
Ground for DSD data output
Bit clock input for DSD data output (open)
Bit clock output for DSD data output
Phase reference signal input for DSD signal phase modulation (open)
Phase reference signal output for DSD signal phase modulation (open)
Lch zero data detection flag signal output (open)
Lch DSD data output
Rch zero data detection flag signal output (open)
Rch DSD data output
• IC801
CXD2752R (PLAYBACK SIGNAL PROCESSOR) (DVD BOARD)
68
HCD-S500/S800
Pin No.
67
68
69
70
71
72
73
74
75
76
77
78, 79
80
81, 82
83
84, 85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101 to 105
106
107 to 109
110
111 to 114
115
116
117 to 120
121
122
123
124 to 125
126
127
128 to 129
130
131 to 134
135
136 to 139
I/O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
O
O
O
I
I
I
O
I
I
I
I
I
I
I
I
I
I/O
I/O
Pin Name
VDDSD0
ZDFC
DSAC
ZDFLFE
DSALFE
VSDSD1
ZDFLS
DSALS
ZDFRS
DSARS
VDDSD1
IOUT0 - 1
VSCB0
IOUT2 - 3
VDCB0
IOUT4 -5
VSIOB0
IANCO
IFULL
IEMPTY
VDIOB0
IFRM
IOUTE
IBCK
VSCB1
IERR
IANCI
IPLAN
IHOLD
VDCB1
IVLD
IDIN0 - 4
VSIOB1
IDIN5 -7
VDIOB1
WAD0 - 3
TESTI
VSCB2
WAD4 - 7
VDCB2
WRFD
WCK
WAVDD0 - 1
WARFI
WAVRB
WAVSS1 - 0
VSIOA2
DQ7 - 4
VDIOA2
DQ3 - 0
Description
Power supply for DSD data output
Cch zero data detection flag signal output (open)
Cch DSD data output
LFEch zero data detection flag signal output (open)
LFEch DSD data output
Ground for DSD data output
LSch zero data detection flag signal output (open)
LSch DSD data output
RSch zero data detection flag signal output (open)
RSch DSD data output
Power supply for DSD data output
Output terminal for test (open)
Ground
Output terminal for test (open)
Power supply
Output terminal for test (open)
Ground for I/O
Output terminal for test (open)
Input teminal for test (connected to ground)
Input teminal for test (connected to ground)
Power supply for I/O
Output terminal for test (open)
Output terminal for test (open)
Output terminal for test (open)
Ground
Input teminal for test (connected to Vdd)
Input teminal for test (connected to ground)
Input teminal for test (connected to Vdd)
Output terminal for test (open)
Power supply
Input teminal for test (connected to ground)
Input teminal for test (connected to ground)
Ground for I/O
Input teminal for test (connected to ground)
Power supply for I/O
External A/D data input for PSP physical disc mark detection
Input teminal for test (pull-down)
Ground
External A/D data input for PSP physical disc mark detection
Power supply
Input teminal for test (connected to ground)
Clock input for PSP physical disc mark detection
A/D power supply for PSP physical disc mark detection (+2.5v)
Analog RF signal input for PSP physical disc mark detection
A/D bottom reference input for PSP physical disc mark detection
A/D ground for PSP physical disc mark detection
Ground for I/O
SDRAM data input/output terminal
Power supply for I/O
SDRAM data input/output terminal
69
HCD-S500/S800
Pin No.
140
141
142
143
144
145
146
147
148, 149
150
151, 152
153
154 to 157
158
159 to 162
163
164
165
166
167
168
169 to 176
I/O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
Pin Name
VSIOA3
DCLK
DCKE
XWE
XCAS
XRAS
VDIOA3
NC
A11 -10
VSCA3
A9 - 8
VDCA3
A7 - 4
VSIOA4
A3 - 0
VDIOA4
XSRQ
XSHD
SDCK
XSAK
SDEF
SD0 -7
Description
Ground for I/O
Clock output terminal for SDRAM
Clock enable signal output for SDRAM
Write enable signal output for SDRAM
Column address strobe signal output for SDRAM
Row address strobe signal output for SDRAM
Ground for I/O
Output terminal for test (open)
Address signal output for SDRAM
Ground
Address signal output for SDRAM
Power supply
Address signal output for SDRAM
Ground for I/O
Address signal output for SDRAM
Power supply for I/O
Data request output to the front end processor
Headder flag input from the front end processor
Data transfer clock input from the front end processor
Data effective flag input from the front end processor
Error flag input from the front end processor
Stream data input from the front end processor
NOTE:
• -XX, -X mean standardized parts, so they may
have some difference from the original one.
• Items marked “*” are not stocked since they
are seldom required for routine service. Some
delay should be anticipated when ordering
these items.
• The mechanical parts with no reference
number in the exploded views are not supplied.
• Hardware (# mark) list and accessories and
packing materials are given in the last of this
parts list.
• Abbreviation
AR
: Argentina model
AUS
: Australian model
CND
: Canadian model
EA
: Saudi Arabia model
E12
: 220-240V AC area in E model
E32
: 110-240V AC area in E model
HK
: Hong Kong model
KR
: Korean model
MX
: Mexican model
MY
: Malaysia model
SP
: Singapole model
TW
: Taiwan model
SECTION 7
EXPLODED VIEWS
70
HCD-S500/S800
The components identified by mark 0 or
dotted line with mark 0 are critical for safety.
Replace only with part number specified.
Les composants identifiés par une marque
0 sont critiques pour la sécurité.
Ne les remplacer que par une pièce portant
le numéro spécifié.
1
X-4952-564-1 KNOB (VOL) ASSY
2
X-4953-853-1 LID WINDOW SUB ASSY
3
4-234-909-01 DVD LID
4
4-221-580-01 SCREW, CASE
5
4-234-913-01 CASE
6
4-217-350-11 STOPPER, CORD
Ref. No.
Part No.
Description
Remark
Ref. No.
Part No.
Description
Remark
0 7
1-690-608-11 CORD, POWER (E12,E32,AUS)
0 7
1-696-169-21 CORD, POWER (AEP,CIS,UK,EA,MY,SP,HK,TW)
0 7
1-769-079-21 CORD, POWER (KR)
0 7
1-775-789-91 CORD, POWER (MX)
0 7
1-783-532-11 CORD, POWER (US,CND)
0 7
1-783-941-21 CORD, POWER (AR)
7-1. MAIN SECTION
1
2
3
4
5
6
7
4
#1
#1
Front panel section
Chassis section

Click on the first or last page to see other DAV-S500 / DAV-S800 / HCD-S800 service manuals if exist.