Read Sony DAV-DZ530 / DAV-DZ630 / HCD-DZ530 / HCD-DZ630 Service Manual online
61
HCD-DZ530/DZ630
Pin No.
Pin Name
I/O
Description
48
RESERVED
—
USB port DMINUS pin for HS DL (not used (Open))
49
USB_VDD3
—
Power supply (SW+3.3V)
50
SPFG
I
Spindle FG input
51
MSW
O
DVD/CD switch (H:DVD / L:CD)
52
CKSW
I
CKSW input
53
OCSW
I
OCSW input
54
EEWP
O
EEPROM Write Protect control (L:Write allowed)
55
DVDD18
—
Power supply (+1.8V from IC1110)
56 to 64
HA2 to 8, 18, 19
O
Host address bus 2 to 8, 18, 19 output to Flash ROM (IC1102)
65
DVDD3
—
Power supply (SW+3.3V)
66
XWR
O
Write enable output to Flash ROM (IC1102) (active Low)
67 to 75
HA16 to 9, 20
O
Host address bus 15 to 9, 20 output to Flash ROM (IC1102)
76
XROMCS
O
Chip select output to Flash ROM (IC1102) (active Low)
77
HA1
O
Host address bus 1 output to Flash ROM (IC1102)
78
XRD
O
Read enable output to Flash ROM (IC1102) (active Low)
79, 80
HD0,1
I/O
Host data bus 0,1 input/output for Flash ROM (IC1102)
81
DVSS
—
Ground terminal
82 to 86
HD2 to 6
I/O
Host data bus 2 to 6 input/output for Flash ROM (IC1102)
87
HA21
O
Host address bus 21 output to Flash ROM (IC1102)
88
RESERVED
—
Not used (Open)
89
HD7
I/O
Host data bus 7 input/output for Flash ROM (IC1102)
90
DVSS
—
Ground terminal
91, 92
HA17, 0
O
Host address bus 17, 0 output to Flash ROM (IC1102)
93
DVDD18
—
Power supply (+1.8V from IC1110)
94
RESERVED
—
Not used (Open)
95
RESERVED
—
Not used (Open)
96
DVDD3
—
Power supply (SW+3.3V)
97
IFSDO
O
Ext. CPU Serial data output (H/W method)
98
IFCK
O
Ext. CPU Serial clock (H/W method)
99
xIFCS
O
Chip select for Ext.CPU (Low Active, H/W method)
100
IFSDI
I
Ext. CPU Serial data input (H/W method)
101
SCL
O
IIC clock output to E2PROM and HDMI controller
102
SDA
I/O
IIC data input/output for E2PROM and HDMI controller
103
HDMI_SCL
O
HDMI DDC line SCL
104
HDMI_SDA
I/O
HDMI DDC line SDA
105
RXD
I
RS232C RXD signal input from Jig
106
TXD
O
RS232C TXD signal output to Jig
107
ICE
O
ICE mode enable (not used (Open))
108
xSYSRST
I
Reset input from system controller (IC501) (active Low)
109
RESERVED
I
IR control signal input (not used (Open))
110
xTXINT
I
Interrupt signal from HDMI controller (not used (Fixed “H” (SW+3.3V)))
111
DQM0
O
Lower byte mask output to SDRAM (IC1104) (H:Mask / L:Enable)
112
IFBSY
I
Ready/Busy interrupt signal input from system controller (IC501) (H:Busy / L:Ready)
113 to 117
RD7 to 3
I/O
Data bus 7 to 3 input/output for SDRAM (IC1104)
118
DVDD3
—
Power supply (SW+3.3V)
119 to 129
RD2 to 0, 15 to 8
I/O
Data bus 2 to 0, 15 to 8 input/output for SDRAM (IC1104)
130
LIMITSW
I
LIMITSW signal input
131
DVDD3
—
Power supply (SW+3.3V)
132
DQM1
O
Upper byte mask output to SDRAM (IC1104) (H:Mask / L:Enable)
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