Read Sony DAV-C700 / DAV-C900 / HCD-C700 / HCD-C900 Service Manual online
74
HCD-C700/C900
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18 to 25
26
27
28
29
30
31
32 to 34
35
36
37
38 to 41
42
43, 44
45
46, 47
48
49
50
51, 52
53
54
55, 56
57
58
59
60
61
62
63
64
65
66
I/O
–
I
I
I
–
O
O
O
I
I
I
–
O
O
O
O
–
O
I
I
–
O
I
I
I
–
O
O
O
–
O
–
O
O
–
O
I
O
–
O
I
–
I
O
I
O
O
O
O
O
Pin Name
VSCA0
XMSLAT
MSCK
MSDATI
VDCA0
MSDATO
MSREADY
XMSDOE
XRST
SMUTE
MCKI
VSIOA0
EXCKO1
EXCKO2
LRCK
F75HZ
VDIOA0
MNT0 - 7
TCK
TDI
VSCA1
TDO
TMS
TRST
TEST1 - 3
VDCA1
UBIT
XBIT
SUPDT0 - 3
VSIOA1
SUPDT4 - 5
VDIOA1
SUPDT6 - 7
SUPEN
VSCA2
NC
TEST4 - 5
NC
VDCA2
NC
BCKASL
VXDSD0
BCKAI
BCKAO
PHREFI
PHREFO
ZDFL
DSAL
ZDFR
DSAR
Description
Ground
Latch signal input for micom serial communication
Shift clock input for micom serial communication
Data input for micom serial communication
Power supply
Data output for micom serial communication
Output ready flag output for micom serial communication
Output enable signal output for micom serial communication (Not used)
Reset signal input
Soft mute signal input (H:soft mute, L:off)
Master clock input (768Fs 33.8688MHz)
Ground for I/O
External clock output 1
External clock output 2 (Not used)
Clock output (1Fs 44.1kHz)(Not used)
Frame signal output
Power supply for I/O
Monitor signal output (Not used)
Test clock input (connected to ground)
Input terminal for test
Ground
Output terminal for test (open)
Input terminal for test (open)
Reset terminal for test (open)
Input terminal for test (connected to ground)
Power supply
Output terminal for test (open)
DST monitor terminal (open)
Supplementary data output (open)
Ground for I/O
Supplementary data output (open)
Power supply for I/O
Supplementary data output (open)
Supplementary data acknoledge output (open)
Ground
Output terminal for test (open)
Input terminal for test (connected to ground)
Output terminal for test (open)
Power supply
Output terminal for test (open)
Bit clock I/O selection signal input for DSD data output (L:slave, H:master)
Ground for DSD data output
Bit clock input for DSD data output (open)
Bit clock output for DSD data output
Phase reference signal input for DSD signal phase modulation (open)
Phase reference signal output for DSD signal phase modulation (open)
Lch zero data detection flag signal output (open)
Lch DSD data output
Rch zero data detection flag signal output (open)
Rch DSD data output
• IC801
CXD2752R (PLAYBACK SIGNAL PROCESSOR) (DVD BOARD)
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