Read Sony CMT-DH30 / HCD-DH30 Service Manual online
HCD-DH30
64
Pin No.
Pin Name
I/O
Description
60
O-USB SO
O
Ready to send signal output to the USB controller
61
I-USB SI
I
Clear to send signal input from the USB controller
62 to 64
NC
O
Not used
65
O-BT AV ROL
O
Transmission/reception mode notifi cation signal output terminal Not used
66
I-BT CTS
I
Clear to send signal input terminal Not used
67
O-BT RTS
O
Ready to send signal output terminal Not used
68
O-BT REST
O
Reset signal output terminal Not used
69
NC
O
Not used
70
O-SBY LED
O
LED drive signal output terminal for STANDBY indicator "L": LED on
71
I-BT RXD
I
Serial data input terminal Not used
72
O-BT TXD
O
Serial data output terminal Not used
73
O-FL RST
O
Reset signal output to the fl uorescent indicator tube driver "L": reset
74
O-FL CE
O
Chip enable signal output to the fl uorescent indicator tube driver
75
O-POWER
O
Sub power on/off control signal output terminal "H": power on
76
O-XM TXD/O-USB TXD
O
Serial data output to the USB controller
77
I-XM RXD/I-USB RXD
I
Serial data input from the USB controller
78
NC
O
Not used
79
I-USB RXD
I
Serial data input from the USB controller
80
I-BT RXD
I
Serial data input terminal Not used
81
I-RMC
I
SIRCS signal input from the remote control receiver
82
NC
O
Not used
83
I-WAKE UP
I
Wake up signal input terminal
84
O-FL DATA
O
Serial data output to the fl uorescent indicator tube driver
85
O-ST CE
O
Chip enable signal output to the tuner (FM/AM)
86
O-FL CLK
O
Shift clock signal output to the fl uorescent indicator tube driver
87
O-ST DATA
O
Serial data output to the tuner (FM/AM)
88
O-ST CLK
O
Serial data transfer clock signal output to the tuner (FM/AM)
89
TOOL0
I
Writing terminal
90
RESET
I
System reset signal input from the reset signal generator "L": reset
For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H"
For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H"
91
XT2
O
Sub system clock output terminal (32.768 kHz)
92
XT1
I
Sub system clock input terminal (32.768 kHz)
93
FLMD0
I
Flash memory programming mode setting terminal
94
X2
O
Main system clock output terminal (20 MHz)
95
X1
I
Main system clock input terminal (20 MHz)
96
REGC
-
External capacitor connection terminal for regulator output of internal operation
97
VSS
-
Ground terminal
98
EVSS0
-
Ground terminal
99
VDD
-
Power supply terminal (+3.3V)
100
EVDD0
-
Power supply terminal (+3.3V)
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