Read Sony CMT-CP500MD / HCD-CP500MD Service Manual online
61
HCD-CP500MD
7-19.
IC BLOCK DIAGRAMS
IC101, 201 TDA7296
IC307 KA3082
THERMAL
SHUTDOWN
BIPOLAR
TRANSCONDACTANCE
INPUT STAGE
STANDBY/
MUTE
BOOST-
STRAP
MOS GAIN &
LEVEL SHIFTING
STAGE
STBY
-GND
IN–
IN+
IN+ MUTE
NC
BOOSTSTRAP
+VS
–VS
STBY
MUTE
NC
NC
+PWVS
OUT
–PWVS
14 15
12
13
10
11
8 9
6
7
5
3
4
1 2
+
–
MOS
OUTPUT
STAGE
SHORT
CIRCUIT
PROTECTION
GND
OUT1
VCTL
VZ1
VZ2
IN1
IN2
VCC1
VCC2
OUT2
5
6
7
8 9 10
1
2 3
4
DRIVER OUT
PRE DRIVER
LOGIC
SWITCH
TSD
BIAS
CH2/A CH2/B
NF
VCC
CG
NF
ALC
METAL
OUT
PRE
OUT
OUT
TAPE A
/TAPE B
REC
OUT
OUT
REC
IN
CH1/A CH1/B
NF
GND1
M/H
NF
CH2
CH2
ALC
M/N
CH1
GND
GND
CH1
+
–
+
–
+
–
+
–
A/B
GND
METAL
OUT
PRE
OUT
OUT
MIX
OUT
REC
OUT
OUT
REC
IN
IREF
VREF2
VREF1
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
IC401 TA8189N
1
2
3
4
5
+
–
INTERRUPT SIGNAL
GENERATING BLOCK
RESET SIGNAL
GENERATING BLOCK
+
–
GND
INT
RESET
CD
VCC
COM
COM
IC308 M62016L
IC309 BU1924F
5
6
7
8
4
3
2
1
12
11
10
9
13
14
15
16
QUAL
RD
ATA
VREF
MUX
VDD1
VSS1
VSS3
CMP
T2
T1
VSS2
VDD2
XI
XO
(NC)
RCLK
8TH SWITCHED
CAPACITOR FILTER
COMPARATOR
PLL
57kHz
RDS/ARI
PLL
1187.5Hz
BI-PHASE
DECODER
DECODER
DIFFERENTIAL
DECODER
TEST
CLOCK
DIGITAL
ANALOG
ANTI-ALIASING
FILTER
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