Read Sony CFD-S40CP Service Manual online
18
CFD-S40CP
Pin No.
Pin name
I/O
Description
1
VDD3
—
Power supply terminal
2
RAS#
O
Strobe signal for M11B41256A (DRAM) column address output (Active: L)
3
DWE#
O
Write enable signal output to M11B41256A (DRAM) (Active: L)
4 – 12
DA0 – 8
O
Address bus output to M11B41256A (DRAM)
13 – 28
DBUS0 – 15
I/O
Data bus terminal to/from M11B41256A (DRAM)
29
RESET#
I
System reset signal input
30
VSS
—
Ground terminal
31
VDD3
—
Power supply terminal
32 – 39
YUV0 – 7
O
Not used (Open)
40
VSYNC
I/O
Not used (Open)
41
HSYNC
I/O
Not used (Open)
42
CPUCLK
I
System clock signal input from ES3889 (DSP)
43
PCLK2X
I/O
Clock for pixel double signal (27MHz)
44
PCLK
I/O
Clock for pixel signal (13.5MHz)
45
AUX0
I
GFS signal input from CXD3068Q
46
AUX1
O
FOK signal output
47
AUX2
O
CD serial data signal output
48
AUX3
O
CPU interface clock signal output to CXD3068Q
49
AUX4
O
I data request signal output
50
VSS
—
Ground terminal
51
VDD3
—
Power supply terminal
52
AUX6
O
CD serial clock signal output
53
AUX5
O
System data strobe signal output
54
AUX7
O
CD serial chip select signal output
55 – 62
LD0 – 7
I/O
Data bus to/from RISK interface
63
LWR#
O
Not used (Open)
64
LOE#
O
Output enable signal output to RISK interface
65
LCS3
O
Chip enable signal output to HT27C020 (ROM)
66
LCS1
O
Clock signal output to system data
67
LCS0
O
Clock signal output to CXD3068Q (DSP)
68 – 79
LA0 – 11
I/O
Address bus to/from HT27C020 (ROM)
80
VSS
—
Ground terminal
81
VPP
—
Protection voltage terminal
82 – 87
LA12 – 17
I/O
Address bus to/from HT27C020 (ROM)
88
ACLK
I/O
Master clock signal of audio DAC data
89
AOUT/SEL-PLL0
I/O
Serial data to/from audio interface
90
ATCLK
O
Transferring audio bit clock signal output
91
ATFS/SEL-PLL1
O
Sync. signal output of transferring audio frame signal
92
DA9/DOE#
O
Output enable signal output to M11B41256A (DRAM)
93
AIN
I
Serial data input from audio interface
94
ARCLK
I
Bit clock signal input from audio receiver
95
ARFS
I
Frame sync. signal input from audio receiver
96
TDMCLK
I
Serial clock input from CXD3068Q
97
TDMDR
I
Serial data input from CXD3068Q
98
TDMFS
I
Frame sync. signal input from CXD3068Q
99
CAS#
O
Strobe signal for M11B41256A (DRAM) row address output (Active: L)
100
VSS
—
Ground terminal
IC1001 ES3880 MP3 DECOMPRESSION
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