Read Sony CFD-S27 Service Manual online
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Note on Schematic Diagram:
Note:
• All capacitors are in
• All capacitors are in
µ
F unless otherwise noted. pF:
µµ
F
50 WV or less are not indicated except for electrolytics
and tantalums.
and tantalums.
• All resistors are in
Ω
and
1
/
4
W or less unless otherwise
specified.
Note: The components identified by mark
!
or dotted
line with mark
!
are critical for safety.
Replace only with part number specified.
•
U
: B+ Line.
•
H
: adjustment for repair.
• Power voltage is dc 9V and fed with regulated dc power
supply from battery terminal.
• Voltages are taken with a VOM (Input impedance 10 M
Ω
).
Voltage variations may be noted due to normal produc-
tion tolerances.
tion tolerances.
• Waveforms are taken with a oscilloscope.
Voltage variations may be noted due to normal produc-
tion tolerances.
tion tolerances.
• Circled numbers refer to waveforms.
• Signal path.
• Signal path.
J
: CD
CFD-S27
5-5. SCHEMATIC DIAGRAM – MAIN SECTION (2/2) –
1
IC701
#¡
(RFO)
r
WAVEFORMS
1.2
±
0.2
Vp-p
VOLT/DIV : 200mV AC
TIME/DIV : 0.5
TIME/DIV : 0.5
µ
sec
4
IC702
#¡
(MNT3)
VOLT/DIV : 1V AC
TIME/DIV : 50
TIME/DIV : 50
µ
sec
2
IC702
@∞
(XPCK)
VOLT/DIV : 1V AC
TIME/DIV : 0.1msec
TIME/DIV : 0.1msec
5
IC702
#™
(MNT1)
VOLT/DIV : 1V AC
TIME/DIV : 50
TIME/DIV : 50
µ
sec
3
IC702
@•
(RFCK)
VOLT/DIV : 1V AC
TIME/DIV : 50
TIME/DIV : 50
µ
sec
6
IC702
#∞
(XTAO)
VOLT/DIV : 0.2V AC
TIME/DIV : 50nsec
TIME/DIV : 50nsec
4.8Vp-p
242.0
µ
sec
5.3 Vp-p
140.5
µ
sec
5.3Vp-p
140.5
µ
sec
5.3 Vp-p
140.5
µ
sec
1.1 Vp-p
16.9344 MHz
IC701 CXA1782CQ
2
3
4
5
6
7
8
9
10
11
12
48
47
46
45
44
42
41
40
39
38
37
36
35
34
33
32
31
29
28
27
26
25
13
14
15
16
17
18
19
20
21
22
23
24
43
1
30
PD2
PD1
PD
LD
RF –
RFI
CP
CB
CC1
CC2CC2
FOK
RFO
LEVELS
MIRR
FOK
RPC
DFCT
IIL DATA RESISTOR INPUT SHIFT RESISTOR
ADDRESS DECODER
OUTPUT DECODER
HPF COMP
LPF COMP
TOG1-3
BAL1-3
FS1-4
TG1-2
TM1-6
PS1-4
FE AMP
F IY AMP
E IY AMP
TE AMP
BAL1
BAL2
BAL3
T
OG1
T
OG2
T
OG3
WINDOW COMP
ATSC
TZC COMP
FZC COMP
DFCT
TM1
FS4
DFCT
FOCUS PHASE COMPENSATION
FS1
FS2
TC1
TC2
TM3
TM4
TM6
TM6
TM2
I. SET
TRACKING
PHASE COMPENSATION
F .SET
SENS
C. OUT
XRST
DATA
XLT
CLK
VCC
ISET
SLO
SL –
SL +
TEO
FO
FI
FDFCT
FGD
FLB
FEO
FE –
SRCH
TGU
TG2
FSET
TE –
IIL
TTL
IIL
TTL
IIL
TTL
F. BIAS
F
E
EI
GND
TO
LPFI
TI
ATSC
TZC
TDFCT
VC
RF IY AMP1
RF IY AMP2
r
IC BLOCK DIAGRAMS – MAIN SECTION (2/2) –
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