Read Sony CDP-M205 / CDP-M305 Service Manual online
– 7 –
Pin No.
Pin name
I/O
Description.
1
FEO
O
Focus error amplifier output.
Connected internally to the window comparator input for bias adjustment.
2
FEI
I
Focus error input.
3
FDFCT
I
Capacitor connection pin for defect time constant.
4
FGD
I
Ground this pin through a capacitor for cutting the focus servo high-frequency gain.
5
FLB
I
External time constant setting pin for boosting the focus servo low-frequency.
6
FE O
O
Focus drive output.
7
FE M
I
Focus amplifier inverted input.
8
SRCH
I
External time constant setting pin for generating focus search waveform.
9
TGU
I
External time constant setting pin for switching tracking high-frequency gain.
10
TG2
I
External time constant setting pin for switching tracking high-frequency gain.
11
FSET
I
Peak frequency setting pin for focus and tracking phase compensation amplifier.
12
TA M
I
Tracking amplifier inverted input.
13
TA O
O
Tracking drive output.
14
SL P
I
Sled amplifier non-inverted input.
15
SL M
I
Sled amplifier inverted input.
16
SL O
O
Sled drive output.
17
ISET
I
Connect an external capacitance to set the current which determines the Focus search,
Track jump, and Sled kick heights.
18
VCC
I
Positive power supply.
19
LOCK
I
The sled overrun prevention circuit operates when this pin is Low (No pull-up resistance).
20
CLK
I
Serial data transfer clock input from CPU (No pull-up resistance).
21
XLT
I
Lach input from CPU (No pull-up resistance).
22
DATA
I
Serial data input from CPU (No pull-up resistance).
23
XRST
I
Reset input; resets at Low (No pull-up resistance).
24
C.OUT
O
Track number count signal output.
25
SENS1
O
Outputs FZC, DFCT1, TZC, BALH, TGH, FOH, ATSC, and others according to the
command from CPU.
26
SENS2
O
Outputs DFCT2, MIRR, BALL, TGL, FOL,and others according to the command from
CPU.
27
FOK
O
Focus OK comparator output.
28
CC2
I
Input for the defect bottom hold output with capacitance coupled.
29
CC1
O
Defect bottom hold output
Connected internally to the interruption comparator input.
30
CB
I
Connection pin for defect bottom hold capacitor.
31
CP
I
Connection pin for MIRR hold capacitor
MIRR comparator non-inverted input.
32
RF I
I
Input for the RF summing amplifier output with capacitance coupled.
33
RF O
O
RF summing amplifier output
Eye-pattern check point.
34
RF M
I
RF summing amplifier inverted input.
The RF amplifier gain is determined by the resistance connected between this pin and
RFO pin .
35
RFTC
I
External time constant setting pin during RF level control.
36
LD
O
APC amplifier output.
37
PD
I
APC amplifier input.
38
PD1
I
RF I-V amplifier inverted input.
39
PD2
I
Connect these pins to the photo diode A+C and B+D pins.
40
FE BIAS
I
Bias adjustment of focus error amplifier
Leave this pin open for automatic adjustment (not used).
SECTION 5
DIAGRAMS
5-1. IC PIN FUNCTION
IC101 FOCUS/TRACKING/SLED SERVO RF AMP (CXA1992AR)
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