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HBD-E380/E580/E880/E980/T58
78
Pin No.
Pin Name
I/O
Description
AF5
SFCK
O
Serial data transfer clock signal output terminal Not used
AF6
TDO
O
Serial data output terminal
AF7
TRST_
I
Reset signal input terminal “L”: reset
AF8, AF9
RDQ25, RDQ27
I/O
Two-way data bus with the SD-RAM
AF10
DGND
-
Ground terminal
AF11,
AF12
RDQ30, RDQ20
I/O
Two-way data bus with the SD-RAM
AF13,
AF14
DVCC15_IO_1
-
Power supply terminal (+1.5V)
AF15,
AF16
RA9, RA2
O
Address signal output to the SD-RAM
AF17
DGND
-
Ground terminal
AF18,
AF19
RDQ1, RDQ3
I/O
Two-way data bus with the SD-RAM
AF20
DVCC15_IO_1
-
Power supply terminal (+1.5V)
AF21 to
AF23
RDQ15, RDQ6,
RDQ5
I/O
Two-way data bus with the SD-RAM
AF24
TN_MEMPLL
-
Test terminal
AF25
RDQ16_B
I/O
Two-way data bus with the SD-RAM
AF26
DGND
-
Ground terminal
AF27
RDQS3_B_
O
Data strobe signal (negative) output to the SD-RAM
AF28
RDQS3_B
O
Data strobe signal (positive) output to the SD-RAM
AG1,
AG2
NFD3, NFD0
I/O
Two-way data bus with the NAND fl ash
AG3
NFCLE
O
Command latch enable signal output to the NAND fl ash
AG4
NFWEN
O
Write enable signal output to the NAND fl ash
AG5
SFDI
O
LPF selection signal output to the video amplifi er “L”: 13.5 MHz LPF, “H”: 30 MHz LPF
(HBD-E380: Singapore, Taiwan, Thai/E580/E880: Canadian, Russian, Australian, Mexican,
Singapore, Taiwan, Thai/E980/T58 only)
(HBD-E380: Singapore, Taiwan, Thai/E580/E880: Canadian, Russian, Australian, Mexican,
Singapore, Taiwan, Thai/E980/T58 only)
AG7,
AG8
RDQ16, RDQ19
I/O
Two-way data bus with the SD-RAM
AG9
RDQS2
O
Data strobe signal (positive) output to the SD-RAM
AG10
RDQS3_
O
Data strobe signal (negative) output to the SD-RAM
AG11
RDQ29
I/O
Two-way data bus with the SD-RAM
AG13
RCLK1
O
Clock signal (positive) output to the SD-RAM
AG14
RBA0
O
Bank address signal output to the SD-RAM
AG16
RCKE
O
Clock enable signal output to the SD-RAM
AG17
RDQ0
I/O
Two-way data bus with the SD-RAM
AG19
RDQ9
I/O
Two-way data bus with the SD-RAM
AG20
RDQS0
O
Data strobe signal (positive) output to the SD-RAM
AG21
RDQS1_
O
Data strobe signal (negative) output to the SD-RAM
AG22
RDQ7
I/O
Two-way data bus with the SD-RAM
AG24
RCLK0
O
Clock signal (positive) output to the SD-RAM
AG25
RDQ17_B
I/O
Two-way data bus with the SD-RAM
AG26
DVCC15_IO_1
-
Power supply terminal (+1.5V)
AG27
RDQS2_B
O
Data strobe signal (positive) output to the SD-RAM
AG28
RDQS2_B_
O
Data strobe signal (negative) output to the SD-RAM
AH1
NFD1
I/O
Two-way data bus with the NAND fl ash
AH2
NFCEN
O
Chip enable signal output to the NAND fl ash
AH4
SFDO
O
Serial data output terminal Not used
AH5
SFCS
O
USB VBUS on/off control signal output terminal wireless LAN card “H”: VBUS on
AH7,
AH8
RDQ17, RDQ18
I/O
Two-way data bus with the SD-RAM
AH9
RDQS2_
O
Data strobe signal (negative) output to the SD-RAM
AH10
RDQS3
O
Data strobe signal (positive) output to the SD-RAM
AH11
RDQ28
I/O
Two-way data bus with the SD-RAM
AH13
RCLK1_
O
Clock signal (negative) output to the SD-RAM
AH14
RA3
O
Address signal output to the SD-RAM
AH16,
AH17
RA8, RA10
O
Address signal output to the SD-RAM
AH19
RDQ8
I/O
Two-way data bus with the SD-RAM
AH20
RDQS0_
O
Data strobe signal (negative) output to the SD-RAM
Ver. 1.3
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