LC-52XS1E (serv.man5). Major IC Informations - Sharp TV Service Manual (repair manual). Page 7

LC-52XS1E/RU/LC-65XS1E/RU

5 – 7

7. IC6302 (RH-iXB801WJQZY)

This is a clock generator, which generates 54MHz for STC, 33MHz for CPLD, 33MHz for FPGA and 33MHz for PCI from the crystal oscillator of
27MHz.

  CLOCK-GENERATOR

8. IC6402~6405 (RH-iXC511WJQZQ)

This is a 512Mb DDR2 SDRAM, which operates as the memory for IC6201.

512Mb DDR SDRAM

1

XI

I

Crystal connection. Connect to a 27MHz fundamental mode pullable crystal.

2, 6, 13

GND

 -

Connect to ground.

3, 5, 10, 14, 

15

VDD

 -

Connect to +3.3V.

4

VIN

I

VCXO Voltage Input. Zero to 3.3v analog control voltage for VCXO.

7

54M

O

54.000MHz reference clock output.

8, 9, 11, 12

33M

O

33.000MHz clock output.

16

X2

I

Crystal connection. Connect to a 27MHz fundamental mode pullable crystal.

J8, K8

CK, CK

I

Clock : CK and CK are differential clock inputs.
All address and control input signals are sampled on the crossing of the positive edge of CK and neg-
ative edge of CK.
Output (read) data is referenced to the crossings of CK and CK (both directions of crossing).

K2

CKE

I

Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, 
and device input buffers and output drivers.
Taking CKE Low provides PRECHARGE POWER DOWN and SELF REFRESH 
operation (all bank idle), or ACTIVE POWER DOWN (row ACTIVE in any bank).
CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry.
CKE is asynchronous for SELF REFRESH exit.
After VREF has become stable during the power on and initialization sequence, it must be maintained 
for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must be main-
tained to this input. 
CKE must be maintained high throughput READ and WRITE accesses.
Input buffers, excluding CK, CK and CKE are disabled during POWER-DOWN.
Input buffers, excluding CKE are disabled during SELF REFRESH. 

L8

CS

I

Chip Select : All commands are masked when CS is registered HIGH.
CS provides for external bank selection on systems with multiple banks.
CS is considered part of the command code.

K9

ODT

I

On Die Termination Control : ODT (registered HIGH) enables on die termination resistance internal to 
the DDR2 SDRAM.
For x16 configuration ODT is applied to each DQ, UDQS/UDQS. LDQS/LDQS, UDM and
LDM signal. 
The ODT pin will be ignored if the Extended Mode Register(EMRS(1)) is
programmed to disable ODT.

K7, L7, K3

RAS, CAS, WE

I

Command Inputs : RAS, CAS and WE (along with CS) define the command being
entered.

F3, B3

DM

(LDM,UDM)

I

Input Data Mask : DM is an input mask signal for write data.
Input data is masked when DM is sampled HIGH coincident along with that input data during a 
WRITE access.
DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ and DQS loading.

L2, L3

BA0, BA1

I

Bank Address Inputs : BA0 and BA1 define to which bank an ACTIVE, Read, Write
or PRECHARGE command is being applied.
Bank address also determines if the mode register
or extended mode register is to be accessed during a MRS or EMRS cycle.

M8, M3, M7, N2, 

N8, N3, N7, P2, 
P8, P3, M2, P7, 

R2

A [0 : 12]

I

Address Inputs : Provide the row address for ACTIVE commands, and the column 
address and AUTO PRECHARGE bit for READ/WRITE commands to select one 
location out of the memory array in the respective bank. 
A10 is sampled during a precharge command to determine whether the 
PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH).
If only one bank is to be precharged, the bank is selected by BA0, BA1. 
The address inputs also provide the op-code during a MODE REGISTER SET 
command. 

G8, G2, H7, H3, 

H1, H9, F1, F9, 

C8, C2, D7, D3, 

D1, D9, B1, B9

DQ[0:15]

I/O

Data Input/Output : Bi-directional data bus.