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LC-42XD1E/RU
5 – 3
2. IC1905: VHiSii9023+-1Q
HDMI RECIEVER
Pin No.
Pin Name
I/O
Pin Function
144
Q0
O
24-bit Output Pixel Data Bus.
143
Q1
O
24-bit Output Pixel Data Bus.
142
Q2
O
24-bit Output Pixel Data Bus.
141
Q3
O
24-bit Output Pixel Data Bus.
140
Q4
O
24-bit Output Pixel Data Bus.
137
Q5
O
24-bit Output Pixel Data Bus.
136
Q6
O
24-bit Output Pixel Data Bus.
133
Q7
O
24-bit Output Pixel Data Bus.
132
Q8
O
24-bit Output Pixel Data Bus.
131
Q9
O
24-bit Output Pixel Data Bus.
130
Q10
O
24-bit Output Pixel Data Bus.
129
Q11
O
24-bit Output Pixel Data Bus.
126
Q12
O
24-bit Output Pixel Data Bus.
125
Q13
O
24-bit Output Pixel Data Bus.
124
Q14
O
24-bit Output Pixel Data Bus.
123
Q15
O
24-bit Output Pixel Data Bus.
119
Q16
O
24-bit Output Pixel Data Bus.
118
Q17
O
24-bit Output Pixel Data Bus.
117
Q18
O
24-bit Output Pixel Data Bus.
116
Q19
O
24-bit Output Pixel Data Bus.
113
Q20
O
24-bit Output Pixel Data Bus.
112
Q21
O
24-bit Output Pixel Data Bus.
111
Q22
O
24-bit Output Pixel Data Bus.
110
Q23
O
24-bit Output Pixel Data Bus.
1
DE
O
Data enable.
2
HSYNC
O
Horizontal Sync Output control signal.
3
VSYNC
O
Vertical Syanc Output control signal.
121
ODCK
O
Output Data Clock.
97
XTALIN
I
Crystal Clock Input.
96
XTALOUT
O
Crystal Clock Output.
88
MCLKOUT
O
Audio Master Clock Output.
86
SCK
O
I2S Serial Clock Output.
85
WS
O
I2S Word Select Output.
84
SDO
O
I2S Serial Data Output.
78
SPDIF
O
S/PDIF Audio Output
77
MUTEOUT
O
Mute Audio Output.
104
INT
O
Interrupt Output.
102
RESET#
I
Reset Pin. Active LOW. 5V Tolerant.
32
DSCL0
I
DDC I2C Clock for Port 0. 5V Tolerant.
31
DSDA0
Bi-Di
DDC I2C Data for Port 0. 5V Tolerant.
30
DSCL1
I
DDC I2C Clock for Port 1. 5V Tolerant.
29
DSDA1
Bi-Di
DDC I2C Data for Port 1. 5V Tolerant.
28
CSCL
I
Configuration I2C Clock. 5V Tolerant.
27
CSDA
Bi-Di
Configuration I2C Data. V Tolerant.
103
SCDT
O
Indicates active video at HDMI input port.
107
CLK48B
Bi-Di
Data Bus Latch Enable. 2
34
R0PWR5V
I
Port 0 Transmitter Detect. 5V Tolerant.
33
R1PWR5V
I
Port 1 Transmitter Detect. 5V Tolerant.
101
RSVDL
I
Reserved, must be tied Low.
56
RSVD_A
Bi-Di
Reserved Pin, leave unconnected.
6, 7, 8, 10, 11, 12,
13, 14, 17, 18,
19, 20, 81, 82,
93, 100
13, 14, 17, 18,
19, 20, 81, 82,
93, 100
NC
—
No internal connection.
87
MCLKIN
O
Audio Master Clock Input Reference.
9
EVNODD
O
Indicates Even or Odd field for interlaced formats. Polarity programmable in register.
40
R0XC+
I
TMDS input clock pair. HDMI Port 0.
39
R0XC-
I
TMDS input clock pair. HDMI Port 0.
44
R0X0+
I
TMDS input data pair. HDMI Port 0.
43
R0X0-
I
TMDS input data pair. HDMI Port 0.
48
R0X1+
I
TMDS input data pair. HDMI Port 0.
47
R0X1-
I
TMDS input data pair. HDMI Port 0.
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