Read Sharp LC-42XD10E (serv.man5) Service Manual online
LC-42XD10E/RU
5 – 6
E3
RAMD_9
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_9)
F4
RAMD_8
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_8)
C7
RAMD_7
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_7)
D6
RAMD_6
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_6)
C6
RAMD_5
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_5)
D5
RAMD_4
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_4)
A7
RAMD_3
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_3)
B6
RAMD_2
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_2)
A6
RAMD_1
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_1)
B5
RAMD_0
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_0)
A2
RAMA_12
O
Address bits for DRAM. (Row/Col) (SDRAM-RAMA_12)
A3
RAMA_11
O
Address bits for DRAM. (Row/Col) (SDRAM-RAMA_11)
D8
RAMA_10
O
Address bits for DRAM. (Row/Col) (SDRAM-RAMA_10)
B3
RAMA_9
O
Address bits for DRAM. (Row/Col) (SDRAM-RAMA_9)
A4
RAMA_8
O
Address bits for DRAM. (Row/Col) (SDRAM-RAMA_8)
B4
RAMA_7
O
Address bits for DRAM. (Row/Col) (SDRAM-RAMA_7)
C3
RAMA_6
O
Address bits for DRAM. (Row/Col) (SDRAM-RAMA_6)
C4
RAMA_5
O
Address bits for DRAM. (Row/Col) (SDRAM-RAMA_5)
D4
RAMA_4
O
Address bits for DRAM. (Row/Col) (SDRAM-RAMA_4)
D9
RAMA_3
O
Address bits for DRAM. (Row/Col) (SDRAM-RAMA_3)
AlO
RAMA_2
O
Address bits for DRAM. (Row/Col) (SDRAM-RAMA_2)
B9
RAMA_1
O
Address bits for DRAM. (Row/Col) (SDRAM-RAMA_1)
C9
RAMA_0
O
Address bits for DRAM. (Row/Col) (SDRAM-RAMA_0)
C8
RAMBA_1
O
DRAM bank select (SDRAM-RAM_BA1)
D7
RAMBA_0
O
DRAM bank select (SDRAM-RAM_BA0)
B8
RAMRAS_N
O
DRAM row address strobe (active low) (SDRAM-RAMRAS_N)
A8
RAMCAS_N
O
DRAM column address strobe (active low) (SDRAM-RAMCAS_N)
J1
RAMDM_3
O
DRAM byte mask lines. (SDRAM-RAMDM_3)
J2
RAMDM_2
O
DRAM byte mask lines. (SDRAM-RAMDM_2)
F2
RAMDM_1
O
DRAM byte mask lines. (SDRAM-RAMDM_1)
C5
RAMDM_0
O
DRAM byte mask lines. (SDRAM-RAMDM_0)
B7
RAMWE_N
O
DRAM write enable (active low) (SDRAM-RAMWE_N)
A9
RAMCS_N
O
DRAM chip select (active low) (SDRAM-RAMCS_N)
A1
RAMCKE
O
DRAM clock enable. (SDRAM-RAMCKE)
B2
RAMCLK
O
DRAM clock output. (SDRAM-RAMCLK)
C2
RAMCLK_N
O
DRAM clock output (inverted) (SDRAM-RAMCLK_N)
K2
RAMDQS_3
I/O
Strobe signal. (SDRAM-RAMDQS_3)
H1
RAMDQS_2
I/O
Strobe signal. (SDRAM-RAMDQS_2)
E1
RAMDQS_1
I/O
Strobe signal. (SDRAM-RAMDQS_1)
A5
RAMDQS_0
I/O
Strobe signal. (SDRAM-RAMDQS_0)
B1
RAMCLKIN
I
Clock (RAMCLK) feed back. (SDRAM-RAMCLKIN)
G7
SSTLVREF
I
SSTL2 Reference Voltage. (SDRAM-SSTLVREF)
K20
SCL1
I
12C bus 1clock.
K21
SDA1
I/O
12C bus 1 data.
B18
SCL2
I
12C bus 2 clock. (no used)
C18
SDA2
I/O
12C bus 2 data. (no used)
H17
TRST
I
Test reset.
G17
TMS
I
Test mode select.
G8
TDO
O
Test data output.
G16 TCLK
I
Test
clock.
G9
TDl
I
Test data input.
M20
CADC5
I
CADC analog source input. (KEY-1) (to key-unit)
M21
CADC4
I
CADC analog source input. (TH3001)
L21
CADC3
I
CADC analog source input. (OPCIN)
K22
CADC2
I
CADC analog source input. (KEY-2) (to key-unit)
L22
CADC1
I
CADC analog source input. (SLOW_SW1)
L23
CADC0
I
CADC analog source input. (SLOW_SW2)
N23
DPWM1
O
Display-PWM outputs. (PWMOUT-BRT-INV)
N22
DPWM2
O
-
W23
DPWM3
O
-
W22
VITUFE
O
V sync output of lTUE-FE.
U3
NVM_22
O
NVM_[22:16] upper address bits (to-flash memory)
Pull-up and pull-down resistors must be used for boot-process configuration
Pull-up and pull-down resistors must be used for boot-process configuration
M2
NVM_21
O
NVM_[22:16] upper address bits (to-flash memory)
M4
NVM_20
O
NVM_[22:16] upper address bits (to-flash memory)
L1
NVM_19
O
NVM_[22:16] upper address bits (to-flash memory)
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