LC-42XD10E (serv.man5). Major IC Information - Sharp TV Service Manual (repair manual). Page 25

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LC-42XD10E/RU
5 – 25
P2
EMIRDnotWR
O
External read/write access indicator. Common to all devices.
EMIRW
H3,H2,G2,H4,G4,E2,E1,E3,
H1,D1,D2,C2,G3,C1,B1,A1
EMIDATA[15:0]
I/O
External common data bus.
EMID[15-
0]
D5,C5,D6,B3,A2,B2,A3,B4,
A4,C6,B5,A5,D7,C7,B6,A6,
B7,A7,D9,C9,B9,A9,B10,C1
1
EMIADDR[25:2]
O
External common address bus
EMIA[23-
2]
(D5,C5=N
C)
J3
notEMIREQGNT
O
Bus request/grant indicator
NC
K4
notEMIACKREQ
I
Bus grant/request indicator (5 V tolerant)
L4
EMIBOOTMODE0
I
External power-up port size indicator (5 V tolerant)
G1
EMISDRAMCLK
O
SDRAM clock
EMICLK
J4
EMIFLASHCLK
O
Peripheral clock
NC
W1,U4,U2,U1,R2,R1,T2,T1
PIO0[7:0]
I/O
Parallel input/output pin or alternative function (5 V tolerant)
(U1:MUTE,R2:VIDEOOFF,R1:MDMRESET,T2:FERESET,T1:CIRE-
SET)
AB4,Y2,AA1,Y1,W3,U3,W2,
W4
PIO1[7:0]
I/O
(W2:TVRX,W4:TVTX)
AF3,AD5,AE3,AE5,AF2,Y3,
AA3,AF1
PIO2[7:0]
I/O
(AF3:ASPECT,AD5:IRQ,AA3:GPIO1,AF1:GPIO0)
AE18,AE4,AC16,AC12,AE6,
AC11,AC5,AE12
PIO3[7:0]
I/O
(AE6:TVSCL,AC11:TVSDA,AC5:I2CSCL,AE12:I2CSDA)
AE20,AD20,AF20,AE19,AC
17,AD18,AD17,AF19
PIO4[7:0]
I/O
(AE20:27MHzPWM,)
AC22,AF22,AD21,AC21,AE
21,AC18,AC20,AF21,
PIO5[7:0]
I/O
(AD21:RXD,AC21:TXD,AF21:IR)
AF17
SCLK
O
Serial clock (5 V tolerant)
NC
AE17
PCMDATA1
O
PCM data out (5 V tolerant)
NC
AE16
PCMCLK
I/O
External PCM clock input or internal PCM clock output (5 V tolerant)
NC
AF18
LRCLK
O
Left/right clock (5 V tolerant)
TL4027
AD16
SPDIF
O
Digital audio output (5 V tolerant)
SPDIF
AD26,AB25,AB24,AC25,AE
26,AB23,AE25,AF26,AD25,
AF25,AE24,AF24,AF23,AE2
3
SMIADDR[13:0]
O
SDRAM address bus
SMIA[13-
0]
U26,U25,R23,V26,V25,T23,
V24,V23,W26,W25,Y25,Y26
,Y23,AB26,Y24,AC26
SMIDATA[15:0]
I/O
SDRAM data bus
SMID[15-
0]
T24
notSMICS0
O
SDRAM chip select for 1st SDRAM
SMICS
T25
notSMICS1
O
SDRAM chip select for 2nd 16 Mbit SDRAM
T26
notSMICAS
O
SDRAM column address strobe
SMICAS
R24
notSMIRAS
O
SDRAM row address strobe
SMIRAS
R25
notSMIWE
O
SDRAM write enable
SMIWE
P26
SMIMEMCLKIN
I
SDRAM memory clock input
R26
SMIMEMCLKOUT
O
SDRAM memory clock output
SMICLK
P24
SMIDATAML
O
SDRAM data bus lower byte enable
SMIDQML
P25
SMIDATAMU
O
SDRAM data bus upper byte enable
SMIDQMI
B15,A15,D16,C16,B16,B17,
C17,D17
P1284DATA[7:0]
I/O
1284 AV data (5 V tolerant)
NC
C15
notP1284SELECTIN
I/O
1284 AV control signals (5 V tolerant)
NC
D15
notP1284INIT
I/O
NC
A14
notP1284FAULT
I/O
NC
B14
notP1284AUTOFD
I/O
NC
C14
P1284SELECT
I/O
NC
D14
P1284PERROR
I/O
NC
D13
P1284BUSY
I/O
NC
D12
notP1284ACK
I/O
NC
D11
notP1284STROBE
I/O
NC
T4, R4, T3,R3
INTERRUPT[3:0]
I/O
External interrupts (5 V tolerant)
MODEMI
RQ,
TL4003,
CIIRQ1,
CIIRQ0
AE1
OUTPLEFT
O
Left channel, differential positive current output
LEFTP
AC1
OUTMLEFT
O
Left channel, differential negative current output
LEFTM
AD1
OUTPRIGHT
O
Right channel, differential positive current output
RIGHTP
AB1
OUTMRIGHT
O
Right channel, differential negative current output
RIGHTM
AF12
ROUT
O
Red output
R
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