LC-42RD2E (serv.man5). Major IC Informations - Sharp TV Service Manual (repair manual). Page 22

LC-42RD2E/S/RU

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45, 46

CK

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Clock: CK and /CK are differential clock inputs. All address and control input signals are sam-
pled on the crossing of the positive edge of CK and negative edge of /CK. Output (read) data is 
referenced to the crossings of CK and /CK (both directions of crossing).

46

/CK

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44

CKE

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Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and 
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER 
DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row 
ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF 
REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE 
must be maintained high throughout READ and WRITE accesses. Input buffers, excluding CK, 
/CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are disabled 
during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after 
VDD is applied.

24

/CS

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Chip Select: Enables or disables all inputs except CK, /CK, CKE, DQS and DM.
All commands are masked when Chip Select is registered high.
Chip Select provides for external bank selection on systems with multiple banks.
Chip Select is considered part of the command code.

26

BA0

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Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRE-
CHARGE command is being applied.

27

BA1

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29

A0

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Address Inputs: Provide the row address for ACTIVE commands, and the column address and 
AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory 
array in the respective bank. A10 is sampled during a precharge command to determine 
whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH).
If only one bank is to be precharged, the bank is selected by BA0, BA1.
The address inputs also provide the op code during a MODE REGISTER SET command.
BA0 and BA1 define which mode register is loaded during the MODE REGISTER SET com-
mand (MRS or EMRS).

30

A1

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31

A2

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32

A3

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35

A4

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36

A5

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37

A6

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38

A7

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39

A8

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40

A9

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28

A10

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