LC-40CT2E (serv.man2) - Sharp TV Service Manual (repair manual). Page 24

Main Processor
- High Performance MIPS32 24KEc CPU core
- 32 bit RISC MIPS architecture
- Supports the MIPS16, MIPS-I, MIPS-II and MIPS-III instruction sets
- 16 KByte instruction cache, 16 KByte data cache
- 2 way cache accessing
- EJTAG debug support

Unified Memory Interface
- Supports 16/32 bit bus width DDR2-SDRAM
- Unified CPU/MPEG/Graphics memory
- Supports data rates up to 655 MHz
- Supports 256 ~ 2048 Mbit total memory

ROM/GIO Interface
- Total address area 64Mbyte for ROM
- Supports normal, page and flash ROM
- Supports NOR and NAND flash ROM
- 4 chip select signals for both ROM and GIO
- 16 MByte total address area for GIO
- Up to 4 Gbit NAND
- PCMCIA support

Stream Processor
- Supports MPEG2-TS (DVB)
- Four dedicated transport stream input ports – two serial and two parallel
- One further channel for input of transport streams via a CPU-controlled register
- Total maximum input bit rate of 108 Mbits/sec
- 36 PID filters

• 1 Video PIDs
• 2 Audio PIDs
• 1 PCR PIDs
• 32 general PIDs

- 32 section filters (8-Byte/16-Byte depth) in four configurable banks
- High Speed Data output port for interfacing to external devices
- DVB descrambling support

Descrambler
- Supports DES, 3DES and AES

DMA
- Supports DMA transfer between internal units and DDR2-SDRAM