LC-37RD2E (serv.man6). Major IC Informations - Sharp TV Service Manual (repair manual). Page 23

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LC-32RD2E/RU, LC-37RD2E/RU
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41
A11
I
Address Inputs: Provide the row address for ACTIVE commands, and the column address and 
AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory 
array in the respective bank. A10 is sampled during a precharge command to determine 
whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH).
If only one bank is to be precharged, the bank is selected by BA0, BA1.
The address inputs also provide the op code during a MODE REGISTER SET command.
BA0 and BA1 define which mode register is loaded during the MODE REGISTER SET com-
mand (MRS or EMRS).
23
/RAS
I
Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being entered.
22
/CAS
I
21
/WE
I
20
LDM
I
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is 
sampled HIGH along with that input data during a WRITE access.
DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading 
matches the DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0-Q7; UDM 
corresponds to the data on DQ8-Q15.
47
UDM
I
16
LDQS
I/O
Data Strobe: Output with read data, input with write data. Edge aligned with read data, centered 
in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0-
Q7; UDQS corresponds to the data on DQ8-Q15.
51
UDQS
2
DQ0
I/O
Data input / output pin: Data bus
4
DQ1
I/O
5
DQ2
I/O
7
DQ3
I/O
8
DQ4
I/O
10
DQ5
I/O
11
DQ6
I/O
13
DQ7
I/O
54
DQ8
I/O
56
DQ9
I/O
57
DQ10
I/O
59
DQ11
I/O
60
DQ12
I/O
62
DQ13
I/O
63
DQ14
I/O
65
DQ15
I/O
1, 15, 33/34, 48, 66
VDD/VSS
Power supply for internal circuits and input buffers.
3, 9, 15, 55, 61/5, 
12, 52, 58, 64
VDDQ/VSSQ
Power supply for output buffers for noise immunity.
49
VREF
Reference voltage for inputs for SSTL interface.
14, 17, 19, 25, 42, 
43, 50, 53, 
NC
No connection.
Pin No.
Pin Name
I/O
Pin Function
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