LC-32SH130K (serv.man8). Circuit Descriptions - Sharp TV Service Manual (repair manual). Page 33

The NAND flash 528-byte/ 264-word page is a family of non-volatile flash memories that uses the single 
level cell (SLC) NAND technology. It is referred to as the small page family.

The NAND512R3A2C, NAND512R4A2C, and NAND512W3A2C have a density of 512 Mbits and operate with 
either a 1.8 V or 3 V voltage supply. The size of a page is either 528 bytes (512 + 16 spare) or 264 words 
(256 + 8 spare) depending on whether the device has a x8 or x16 bus width.

The address lines are multiplexed with the Data Input/output signals on a multiplexed x8 or x16 
input/output bus. This interface reduces the pin count and makes it possible to migrate to other densities 
without changing the footprint.

To extend the lifetime of NAND flash devices it is strongly recommended to implement an error 
correction code (ECC). The use of ECC correction allows to achieve up to 100,000 program/erase cycles 
for each block. A write protect pin is available to give a hardware protection against program and erase 
operations.



High density NAND flash memories



512-Mbit memory array



Cost effective solutions for mass storage applications



NAND interface



x8 or x16 bus width



Multiplexed address/ data



Supply voltage: 1.8 V, 3 V



Page size



x8 device: (512 + 16 spare) bytes



x16 device: (256 + 8 spare) words



Block size



x8 device: (16K + 512 spare) bytes



x16 device: (8K + 256 spare) words



Page read/program



Random access: 12 μs (3 V)/15 μs (1.8 V) (max)



Sequential access: 30 ns (3 V)/50 ns (1.8 V) (min)



Page program time: 200 μs (typ)



Copy back program mode



Fast block erase: 2 ms (typ)



Status register

14.1

14.2