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LC-32D44E/S/RU-BK/GY
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14. IC8103 (VHIT3Z18AFG-1Q)
Single Link LCD Receiver
The LVDS is essentially a signaling method used for high-speed transmission of binary data over copper.
It uses a lower voltage swing than other transmission standards. This low voltage differential is what delivers higher data transmission speeds and
inherently greater bandwidth at lower power consumption.
inherently greater bandwidth at lower power consumption.
This new technology not only addresses the needs of today’s high performance data transmission application, but also the needs of future applica-
tion.
tion.
This LVDS receiver IP supports Single Link transmission between Host and Flat Panel Display. The receiver recovers the LVDS data and converts
into CMOS data. An on-chip PLL synchronizes the received clock with the parallel data and then all are transmitted to the parallel output port of the
receiver.
into CMOS data. An on-chip PLL synchronizes the received clock with the parallel data and then all are transmitted to the parallel output port of the
receiver.
Description:
• Supports Single Link (Single Input to Single Output) up to 135MHz dot clock for SXGA+ (input clock frequency: 25 to 135MHz)
• PLL requires no external components
• Clock strobe edge selectable
• Support 10-bit color
• Power down mode
Pin No.
Pin Name
I/O
Function Name
Pin No.
Pin Name
I/O
Function Name
1
PLLAVD
1.5V
E1AVDLIVC
141
SCLK
OUT
BT4VIC1
2
PLLAVS
GND
E1AVSLIVC
142
SDT
I/O
BD4THVIC1
3
VSSAGND45L
GND
Z7RSTAGND45L
143
vext1103
1.5V
SDRAMVDE1
4
VDDSAVCC4
3.3V
Z7RSTAVCC4
144
VDDC
1.5V
VDDC
5
VSSAGND45C
GND
Z7RSTAGND45C
145
RESET
IN
SMTCIF
6
VDDSAVCC5
3.3V
Z7RSTAVCC5
146
CMOS_IN
IN
IBUFDIF
7
BR0_M
OUT
Z7RSDST
147
OS_SEL
IN
TLCHTHDVIC1
8
BR0_P
OUT
Z7RSDST
148
OS_ON
IN
TLCHTHDVIC1
9
BR1_M
OUT
Z7RSDST
149
BANK_SEL
IN
TLCHTHDVIC1
10
BR1_P
OUT
Z7RSDST
150
TEMP[2]
IN
TLCHTHDVIC1
11
BR2_M
OUT
Z7RSDST
151
vgnd87
GND
SDRAMVSE
12
BR2_P
OUT
Z7RSDST
152
TEMP[1]
IN
TLCHTHDVIC1
13
BR3_M
OUT
Z7RSDST
153
TEMP[0]
IN
TLCHTHDVIC1
14
BR3_P
OUT
Z7RSDST
154
REV_MODE
IN
TLCHTHDVIC1
15
BCLK_M
OUT
Z7RSDST
155
HSCAN
IN
TLCHTHDVIC1
16
BCLK_P
OUT
Z7RSDST
156
VSCAN
IN
TLCHTHDVIC1
17
VDDSAVCC4
3.3V
Z7RSTAVCC4
157
vext1105
1.5V
SDRAMVDE1
18
VSSDGND1
GND
Z7RSTDGND1
158
VSS12
GND
VSS12
19
VDDCDVCC1
1.5V
Z7RSTDVCC1
159
SELLVDS
IN
TLCHTHUVIC1
20
VSSAGND45C
GND
Z7RSTAGND45C
160
SSCLK
I/O
BD8SCIF
21
VDDSAVCC5
3.3V
Z7RSTAVCC5
161
EXCLK
IN
IBUFIF
22
BG0_M
OUT
Z7RSDST
162
VDDC
1.5V
VDDC
23
BG0_P
OUT
Z7RSDST
163
VSSAGND1L
GND
Z7LVRAGND1L
24
BG1_M
OUT
Z7RSDST
164
RA_M
IN
Z7LVRXIO
25
BG1_P
OUT
Z7RSDST
165
RA_P
IN
Z7LVRXIO
26
BG2_M
OUT
Z7RSDST
166
RB_M
IN
Z7LVRXIO
27
BG2_P
OUT
Z7RSDST
167
RB_P
IN
Z7LVRXIO
28
BG3_M
OUT
Z7RSDST
168
RC_M
IN
Z7LVRXIO
29
BG3_P
OUT
Z7RSDST
169
RC_P
IN
Z7LVRXIO
30
VDDSAVCC4
3.3V
Z7RSTAVCC4
170
VDDAVDD1L
3.3V
Z7LVRAVDD1L
31
VSSDGND1
GND
Z7RSTDGND1
171
L_VDDPLL1
2.5V
Z7LVRVDDPLL1
32
VDDCDVCC1
1.5V
Z7RSTDVCC1
172
L_VSSPLL1
GND
Z7LVRVSSPLL1
33
VSSAGND45C
GND
Z7RSTAGND45C
173
L_VDDPLL2
2.5V
Z7LVRVDDPLL2
34
VDDSAVCC5
3.3V
Z7RSTAVCC5
174
L_VSSPLL2
GND
Z7LVRVSSPLL2
35
BB0_M
OUT
Z7RSDST
175
L_VDDD
1.5V
Z7LVRVDDD
36
BB0_P
OUT
Z7RSDST
176
L_VSSD
GND
Z7LVRVSSD
37
BB1_M
OUT
Z7RSDST
177
PVDDA1B
2.5V
Z7LVRVDDPLL1*1
38
BB1_P
OUT
Z7RSDST
178
PVDDA2B
2.5V
Z7LVRVDDPLL2*1
39
BB2_M
OUT
Z7RSDST
179
VDDS_L
3.3V
Z7LVRVDDS
40
BB2_P
OUT
Z7RSDST
180
PVSSA1B
GND
Z7LVRVSSPLL1*1
41
BB3_M
OUT
Z7RSDST
181
PVSSA2B
GND
Z7LVRVSSPLL2*1
42
BB3_P
OUT
Z7RSDST
182
VDDC_L
1.5V
Z7LVRVDDC
43
VDDCLCDVDDC
1.5V
Z7RSTVDDC
183
VDDAVDD2
2.5V
Z7LVRAVDD2
44
VSSLCDVSS2
GND
Z7RSTVSS2
184
VSSAGND2
GND
Z7LVRAGND2
45
VSSAGND45R
GND
Z7RSTAGND45R
185
VDDAVDD1R
3.3V
Z7LVRAVDD1R
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