Read Sharp LC-20VM2E (serv.man2) Service Manual online
26
LC-20VM2E
LC-121M2E
LC-150M2E
LC-150M2E
Terminal
Symbol
I/O
Level
Buffer Type
Function
No.
PU/PD[k
Ω
]
58
SLA0
I
TTL
5V withstand
I
2
C bus slave address selection input
voltage
(L: B8/B9h, H: BA/BBh)
PD:50
59
SCL
I
Schmitt
5V withstand
I
2
C bus clock input
voltage
(Connect to system’s SCL line)
60
SDA
I/O
Schmitt
5mA/5V
I
2
C bus data input/output
Not Open drain withstand voltage (Connect to system’s SDA line)
61
ST0
O
TTL
1mA
Internal signal monitor output
62
ST1
O
TTL
1mA
Internal signal monitor output
63
NSTD
O
TTL
1mA
Nonstandard detection monitor output
(L: Standard decision H: Nonstandard decision)
(L: Standard decision H: Nonstandard decision)
65, 66
DYCO0-DYCO1 I/O
TTL
1mA/5V
EXADINS=0: Digital YC signal alternate output
(LSB)-(MSB)
withstand voltage (lower 2-bit)
EXADINS=1: Test input
(GND connection through resister)
(GND connection through resister)
67-74
DYCO2-DYCO9 I/O
TTL
1mA/5V
EXADINS=0: Digital YC signal alternate output
(LSB)-(MSB)
withstand voltage (upper 8-bit)
EXADINS=1: 8-bit data input for external
Y-ADC
Y-ADC
75
ALTF
O
TTL
1mA
EXADINS=0: Digital YC signal alternate flag
output (L:Y, H:C)
EXADINS=1: 4fsc clock output for external
Y-ADC
output (L:Y, H:C)
EXADINS=1: 4fsc clock output for external
Y-ADC
76
CSI
I
Schmitt
5V withstand
Composite sink input
voltage
(Active low)
PD:50
77
TEST
I
TTL
5V withstand
Test terminal for IC selection
voltage
(L: Normal operation, H: Test mode)
PD:50
(GND connection)
78
LINE
I
TTL
5V withstand
Forced line process selection input
voltage
(L: Normal process, H: Forced line process)
PD:50
79
KIL
I
TTL
5V withstand
External killer input
voltage
(L: Normal process, H: Forced YC separation
PD:50
stop)
81
AVDD
-
-
Y-DAC, C-DAC power supply
82
CBPC
O
Analog
C-DAC phase compensation output
83
ACO
O
Analog
C-DAC analog C signal output
84
AYO
O
Analog
Y-DAC analog Y signal output
85
CBPY
O
Analog
Y-DAC phase compensation output
86
AGND
-
-
Y-DAC, C-DAC ground
87
AGND
-
-
Y-ADC ground
88
AYI
I
Analog
Y-ADC analog composite signal /Y signal input
89
VCLY
O
Analog
Y-ADC clamp potential output
90
VRBY
O
Analog
Y-ADC bottom reference voltage output
91
VRTY
O
Analog
Y-ADC top reference voltage output
92
AVDD
-
-
Y-ADC, C-ADC power supply
93
AVDD
-
-
Y-ADC, C-ADC power supply
94
VRTC
O
Analog
C-ADC top reference voltage output
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