Read Sharp LC-20SD4E (serv.man5) Service Manual online
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IC3001
SN74LVC373APWR
LOGIC IC
1
10
11
12
13
14
15
16
17
18
19
2
20
3
4
5
6
7
8
9
IC3003
SN74LVC245APWR
LOGIC IC
1
10
11
12
13
14
15
16
17
18
19
2
20
3
4
5
6
7
8
9
IC3004
SN74LVC244APWR
LOGIC IC
1
10
11
12
13
14
15
16
17
18
19
2
20
3
4
5
6
7
8
9
IC3002
SN74LVC373APWR
LOGIC IC
1
10
11
12
13
14
15
16
17
18
19
2
20
3
4
5
6
7
8
9
CP3001
36_5027_068_130_831+
1
10
11
12
13
14
15
16
17
18
19
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25
26
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29
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22
23
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25
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3
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59
51
52
53
54
55
56
57
58
59
6
60
61
62
63
64
65
66
67
68
61
62
63
64
65
66
67
68
7
8
9
8
9
CP3002 30_5027_000_102_000+
PCMCIA CARD EJECTOR
Q3002
KTA1664-Y-RTF/P
VCC SW
C3007
100
6.3V
V-S
C3005
100
4V
4V
V-S
IC3005
74LVC1G08GV
DH
AND GATE
1
2
3
4
5
IC3008
74LVC1G32GV
DH
OR GATE
1
2
3
4
5
IC3007
74LVC1G32GV
DH
OR GATE
1
2
3
4
5
IC3006 SN74AHC1G02DCKR
DH
NOR GATE
1
2
3
4
5
Q3001
KTC3875S_Y_RTK
SW
R3002
47
R3001
47
R3010
47
R3009
470
R3007
10K
R3005
1.2K
R3008
47K
R3012
10K
R3004
10K
R3003
10K
R3006
10K
R3011
10K
R3016
10K
R3015
10K
R3014
10K
R3013
10K
C3002
0.1 B
C3003
0.1 B
C3004
0.1 B
C3001
0.1 B
C3006
0.1
B
NR3016
4D02WGJ0470TCE
NR3017
4D02WGJ0470TCE
NR3018
4D02WGJ0470TCE
NR3008
4D02WGJ0470TCE
NR3009
4D02WGJ0470TCE
NR3010
4D02WGJ0470TCE
NR3011
4D02WGJ0470TCE
NR3012
4D02WGJ0470TCE
NR3013
4D02WGJ0470TCE
NR3014
4D02WGJ0470TCE
NR3015
4D02WGJ0470TCE
NR3007
4D02WGJ0470TCE
NR3005
4D02WGJ0470TCE
NR3006
4D02WGJ0470TCE
NR3003
4D02WGJ0470TCE
NR3004
4D02WGJ0470TCE
NR3002
4D02WGJ0470TCE
NR3001
4D02WGJ0470TCE
B3001
FCM1608CF-600T06
OF PRINTING AND SUBJECT TO CHANGE WITHOUT NOTICE
NOTE: THIS SCHEMATIC DIAGRAM IS THE LATEST AT THE TIME
WAS RECEIVED IN GOOD CONDITION AND PICTURE IS NORMAL.
WITH THE DIGITAL TESTER WHEN THE COLOR BROADCAST
NOTE:THE DC VOLTAGE AT EACH PART WAS MEASURED
EMIA[2]
CID[4]
EMIA[3]
CID[5]
EMIA[4]
CID[6]
EMIA[5]
CID[7]
EMIA[6]
EMIA[7]
EMIA[8]
EMIA[7]
EMIA[8]
CIDDIR
EMIA[9]
CIA[10]
EMIA[10]
CIA[11]
EMIA[11]
EMIDM[3]
CICE
CIA[9]
EMIA[12]
CIA[0]
CIA[1]
EMIDM[2]
CIA[8]
EMIA[13]
EMIDM[1]
EMIA[14]
EMIDM[0]
CID[3]
CIIORD
EMIA[15]
EMIA[2]
CIOE
EMIA[16]
EMIA[3]
CIDDIR
CIA[13]
EMIA[18]
EMIA[4]
CID[2]
CIA[14]
EMIBE0
EMIA[5]
CIA[12]
EMILBA
CION
CID[1]
CPUWAIT
CIA[3]
CIA[2]
CIIRQ0
CIIRQ1
CIIRQ1
CIA[7]
EMIDM[7]
CID[0]
CIRESET
CIA[6]
CIA[4]
CIA[5]
EMIDM[6]
EMICS3
CIA[5]
EMIDM[5]
TS2STRT
CIA[4]
EMIDM[4]
CID[4]
TS2CLK
EMIA[6]
TS2VAL
EMIA[7]
TS2D[7]
EMIA[8]
CID[5]
CIA[3]
TS2D[6]
EMIA[9]
CIA[2]
TS2D[5]
CPUWAIT
CIA[1]
TS2D[4]
CID[6]
CIWAIT
CIA[0]
TS2D[3]
CIA[7]
CIA[6]
TS2D[0]
TS2D[1]
TS2D[1]
CID[7]
TS2D[2]
CID[3]
CID[0]
CID[1]
CID[2]
CID[0]
CID[1]
CID[2]
CICE
TS2D[4]
TS2D[5]
TS2D[5]
EMIDM[0]
TS2D[6]
EMIDM[1]
TS2D[7]
EMIDM[2]
EMIDM[3]
EMIDM[4]
EMIDM[3]
EMIDM[4]
CICD2
EMIDM[5]
CICD1
FEVALID
EMIDM[6]
FECLK
EMIDM[7]
CIIRQ0
FESTROUT
EMIOEM
EMIRASM
EMICASM
EMICASM
EMIOEM
CIA[8]
CIA[9]
FED[0]
CIOE
EMIA[10]
FED[1]
EMIA[11]
FED[2]
EMIA[12]
FED[3]
EMILBA
EMIA[13]
FEVALID
CION
FECLK
FED[0]
CIWE
CIA[11]
CIA[10]
FED[1]
FED[4]
FED[2]
FED[5]
EMIRASM
FED[3]
FED[6]
CIA[12]
CIA[13]
FED[4]
FED[7]
FED[5]
FED[6]
FED[6]
CIIORD
EMIA[14]
FED[7]
EMIA[15]
FESTROUT
TS2CLK
EMIA[16]
EMICASM
TS2VAL
EMIA[18]
TS2STRT
CIIOWR
CIREG
CIA[14]
TS2D[3]
CIWAIT
CIIOWR
CIIORD
CICD1
CIWE
CIOE
CICE
CIREG
CICD2
EMICS3
TS2D[0]
EMIBE0
TS2D[1]
CICE
TS2D[2]
GND
P5V
P3V3
P3V3CI
CIRESET
CIIRQ1
P5VPCMCIA
H-34
H-33
FROM/TO ASIC
FROM/TO FLASH/SDRAM
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
CI Connecotr
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
VCC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
LE
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
VCC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
LE
1G
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
VCC
2G
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
DIR
A1
A3
A4
A5
A6
A7
A8
GND
VCC
0E
B1
B2
B3
B4
B5
B6
B7
B8
A2
INB
INA
GND
OUT
VCC
INB
INA
GND
OUT
VCC
INB
INA
GND
OUT
VCC
GND
D3
D4
D5
D6
D7
D4
D5
D6
D7
CE1
A10
A10
OE
A11
A9
A8
A8
A13
A14
A14
WE/PGM
IREQ
VCC
VPP1
MIVAL
MICLK
MICLK
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
IOCS16
GND
GND
CD1
GND
CD1
MOD3
MOD4
MOD5
MOD6
MOD7
MOD4
MOD5
MOD6
MOD7
CE2
VTGSENS
IORD
IOWR
IOWR
MISTRT
MDI0
MDI1
MDI2
MDI3
MDI1
MDI2
MDI3
VCC
VPP2
MDI4
MDI5
MDI6
MDI7
MDI4
MDI5
MDI6
MDI7
MOCLK
RESET
RESET
WAIT
INP_ACK
REG
MOVAL
MOSTRT
MOD0
MOD1
MOD2
MOD1
MOD2
CD2
GND
GND
3.3
0.1
3.2
0.7
0
0
0.7
1.0
0
0
3.3
0
0.5
2.5
0
0
2.7
3.0
0
3.3
3.3
0.2
2.4
3.0
0.3
0.2
0
0.3
0
3.3
0
0
0.1
2.4
0
0.1
0.8
0.8
0
3.3
3.3
3.3
0.2
3.3
0.2
3.3
0.2
3.2
0
0
0
0
0
0
0
0
0
0
3.3
3.3
0
0
0
0
0
0
0
0.3
0.3
3.3
0.2
0.2
0.3
0.3
0.3
0.3
0.2
0.2
3.3
3.3
0.3
0.3
0
3.3
3.3
5.0
5.0
0
3.3
3.3
5.0
4.2
5.0
0
0
5.7
3.3
3.2
0
3.3
3.3
FROM/TO POWER I/O
FROM/TO OFDM/TUNER
PCBDH0
CEF196
CEF196
COMMON INTERFACE SCHEMATIC DIAGRAM
(DIGITAL PCB)
NC
NC
NC
NC
INB
INA
GND
OUT
VCC
5.0
0
0
3.3
0
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