76FW-54H. DA100 Repair Notes - Sharp TV Service Manual (repair manual). Page 50

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DA100 (50Hz) Chassis – Article for Television Magazine 
Control and Communication 
As with all current Sharp television chassis, the microprocessor (CPU) is responsible for the control of 
the set, communicating with all other areas of the chassis via various data buses. Similar to other 
chassis the CPU does not operate during standby.  As there needs to be some form of control on the 
primary side of the power supply, a slave processor is used.  This slave processor has a volatile 
memory, therefore each time power is applied to the television the switch mode powers supply has to 
start, enabling the slave processor program to be downloaded from the OTP before switching to 
standby. 
Figure 50: Communication Block Diagram 
Communication Lines 
There are several types of communication lines that provide information to the CPU, and are used to 
control the various devices connected to it.  These are as follows.   
Parallel Bus  
This provides communication between the CPU and the ROM (OTP, MTP or EPROM). This device 
contains the software (operating system) 
I2C Bus  
There are two I2C buses, I2C(2) is used to communicate with the NVM’s (EPROM’s), these devices 
contain data relating to all adjustments, whether it is an end user adjustment, service adjustment or 
an automatic setting performed by the CPU.  I2C(1) provides serial data communications between the 
CPU and Tuner, Video Processor, Multiple Sound Processor and the Dolby Processor (if fitted). 
M3 Bus 
This bus line provides data communication between CPU and the Megatext processor. 
Page 50 of 80 
Sharp Electronics (UK) Limited - March 2003 
Revision 2
 
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