Read Sharp 76FW-53H (serv.man13) Service Manual online
Colour Television – DA100/DW100 Chassis
Sharp Electronics (UK) Ltd
Technical Support
September 99
Page 17
MICROPROCESSOR CONTROL
The microprocessor (CPU) is at the hart of this CTV, communicating with all other area via various
data buses. Similar to the CS, CA10 and CW100 chassis this CPU is not operating during standby,
therefore contained in the primary side of the power supply there is a slave processor. This slave
processor has a volatile memory, therefore each time power is applied to this CTV the switch mode
powers supply has to start enabling the slave processor program to be downloaded from the OTProm
before switching to standby.
data buses. Similar to the CS, CA10 and CW100 chassis this CPU is not operating during standby,
therefore contained in the primary side of the power supply there is a slave processor. This slave
processor has a volatile memory, therefore each time power is applied to this CTV the switch mode
powers supply has to start enabling the slave processor program to be downloaded from the OTProm
before switching to standby.
P
ARALLEL
B
US
Communication between the CPU and the OTProm (one time programmable read
only memory). This device contains the software (operating system)
I2C
BUS
There are two I
2
C buses, I
2
C(2) communicates between the NVM’s (eeprom), these
devices contains data relating to all adjustments, whether it is an end user
adjustment, service adjustment or an automatic setting performed by the CPU. I
adjustment, service adjustment or an automatic setting performed by the CPU. I
2
C(1)
provides serial data communications between the CPU and Tuner, Video Processor,
Multi Sound Processor and the Dolby Processor (if fitted).
Multi Sound Processor and the Dolby Processor (if fitted).
M3
BUS
Data communication between CPU and the teletext processor (MegaText)
S
LAVE
Data bus to the slave processor an a data us from the slave processor.
R
ESET IN
Main system reset, this will operate each time the main switch mode powers supply
starts. Reset is a state change from low to high generated by IC1005.
starts. Reset is a state change from low to high generated by IC1005.
R
ESET OUT
(1)
IC801 reset (low). If IC801 is not reset then the line oscillator will not function. This will
only occur after reset in.
only occur after reset in.
R
ESET OUT
(2)
Resets all other areas of this CTV, this will only occur after reset out (1). Teletext
reset is inverted.
reset is inverted.
P
ROTECTION
If the CPU pin 96 goes low the CTV will switch to standby. This is trigged by one of
the audio output stages or excessive beam current.
the audio output stages or excessive beam current.
Dolby
Processor
Processor
Video/Sync
Processor
Processor
Tuner
Multi-Sound
Processor
Processor
I2C Bus (2)
I2S Bus
NVM
(eeprom)
(eeprom)
NVM
(eeprom)
(eeprom)
I2C Bus (1)
Slave
Processor
Processor
MegaText
M3 Bus
IC1001
(CPU)
(CPU)
OTP
Main Reset
Reset out (1)
Reset out (2)
AV Link Data
Reset out (2)
AV Link Data
AV Link Clock
AFT-1
AFT-2
AFT-2
IF
IC2028
Protection
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