Read Sharp 66DW-18H (serv.man3) Service Manual online
Wide Screen, Colour Television CW100 Chassis
Sharp Electronics (UK) Ltd
Technical Support
February 99
Page 22
VPROT:
Vertical saw-tooth voltage
Vi < V1 in first half of V-period or
Vi > V2 in second half: HD disabled
Vi < V1 in first half of V-period or
Vi > V2 in second half: HD disabled
The pin SCP (Sandcastle) delivers the composite blanking signal SCP. It contains burst (
Vb ), H-
blanking HBL (
VHBL ) V-blanking. The phase of the H-blanking period can be varied by I
2
C Bus.
The system clock for the SDA 9362 has to be generated externally and is applied to pin1 'CLL'. Its
frequency must be always be the same as the line frequency (defined by the horizontal time reference
HSYNC) multiplied by 864. If no HSYNC signal is available an internal horizontal synchronization
signal is derived from CLL (CLL divided by 879).
frequency must be always be the same as the line frequency (defined by the horizontal time reference
HSYNC) multiplied by 864. If no HSYNC signal is available an internal horizontal synchronization
signal is derived from CLL (CLL divided by 879).
The input signal at VSYNC is the vertical time reference. It has to pass a window avoiding too short or
long V-periods in the case of distorted or missing VSYNC pulses. The window allows a VSYNC pulse
only after a minimum number of lines from its predecessor and sets an artificial one after a maximum
number of lines. The window size is programmable by I
long V-periods in the case of distorted or missing VSYNC pulses. The window allows a VSYNC pulse
only after a minimum number of lines from its predecessor and sets an artificial one after a maximum
number of lines. The window size is programmable by I
2
C Bus.
The beam-current dependent input signal IBEAM is A/D converted and then digitally processed. The
A/D Converter requires a clock frequency twice the frequency of CLL. This is generated by an internal
analog PLL with an external loop filter at pin LF. Values, which influence shape and amplitude of the
output signals, are transmitted as reduced binary values to the SDA 9362 via I
A/D Converter requires a clock frequency twice the frequency of CLL. This is generated by an internal
analog PLL with an external loop filter at pin LF. Values, which influence shape and amplitude of the
output signals, are transmitted as reduced binary values to the SDA 9362 via I
2
C Bus. A CPU which is
designed for speed reasons in a pipe line structure calculates in consideration of feedback signals
(e.g. IBEAM) values which exactly represent the output signals. These values control after D/A
conversion the external deflection and raster correction circuits. The CPU firmware is stored in an
internal ROM.
(e.g. IBEAM) values which exactly represent the output signals. These values control after D/A
conversion the external deflection and raster correction circuits. The CPU firmware is stored in an
internal ROM.
Figure 1 Sync Processor Block Diagram
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