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MX-C401 CIRCUIT DIAGRAM AND PARTS LAYOUT / 回路図と部品配置図 2 – 99
MFP_LSU_K0
MFP_LSU_K1
MFP_LSU_K2
MFP_LSU_K3
MFP_LSU_K4
MFP_LSU_K5
MFP_LSU_C0
MFP_LSU_C1
MFP_LSU_C2
MFP_LSU_C3
MFP_LSU_C4
MFP_LSU_C5
MFP_LSU_M0
MFP_LSU_M1
MFP_LSU_M2
MFP_LSU_M3
MFP_LSU_M5
MFP_LSU_M4
MFP_LSU_Y1
MFP_LSU_Y0
MFP_LSU_Y3
MFP_LSU_Y4
MFP_LSU_Y2
MFP_LSU_Y5
SCN_DAT_R0
SCN_DAT_R1
SCN_DAT_R2
SCN_DAT_R3
SCN_DAT_R4
SCN_DAT_R5
SCN_DAT_R
6
SCN_DAT_R
7
SCN_DAT_G2
SCN_DAT_G3
SCN_DAT_G4
SCN_DAT_G5
SCN_DAT_G
6
SCN_DAT_G
7
SCN_DAT_G0
SCN_DAT_G1
SCN_DAT_B0
SCN_DAT_B1
SCN_DAT_B2
SCN_DAT_B3
SCN_DAT_B4
SCN_DAT_B5
SCN_DAT_B
6
SCN_DAT_B
7
SCN_FBCLK
LSHSYNCM_OUT
LSHSYNCY_OUT
LSHSYNCC_OUT
MFP_LSU_K
6
MFP_LSU_K
7
MFP_LSU_C
6
MFP_LSU_C
7
MFP_LSU_M
6
MFP_LSU_M
7
MFP_LSU_Y
6
MFP_LSU_Y
7
LSU_CLK_OUT
3R3V_ECO
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
LSCLK
{30
}
SCN_DAT_R
[7
:0
]
{31
}
SCN_DAT_G
[7
:0
]
{31
}
SCN_DAT_B
[7
:0
]
{31
}
SCN_CLK
{24
,31
}
MFP_LSU_K
[7
:0
]
{30
}
MFP_LSU_C
[7
:0
]
{30
}
MFP_LSU_M
[7
:0
]
{30
}
MFP_LSU_Y
[7
:0
]
{30
}
JTAG_CK2_ECO
{24
,35
,3
6,
40
}
MFP_
JTAG_TDI
{35
}
JTAG_TMS2_ECO
{24
,35
,3
6,
40
}
JTAG_RST2_ECO
{35
,3
6,
40
}
MFP_
JTAG_TDO
{35
}
LSHSYNC_IN
{30
}
MFP_LSU_CLK
{30
}
LSVSYNC_C
{30
}
LSVSYNC_M
{30
}
LSVSYNC_Y
{30
}
LSVSYNC_K
{30
}
MFP_REFCLK
{5
}
SSYNC_SIOUT
{24
}
HSYNC_SIOUT
{24
}
LINGT_SIOUT
{24
}
DOTGT_SIOUT
{24
}
MFP_LSU_HSYNC
{30
}
CP58CP58
CP
77
CP
CP
77
CP80CP80
CP
6
1
CP
6
1
CP8
7
CP8
7
C82
0.1uF(B)
C82
0.1uF(B)
RB
77
10
J
RB
77
10
J
R51
10K
J
R51
10K
J
CP81CP81
CP
6
4
CP
6
4
CP
76
CP
CP
76
CP
6
0
CP
6
0
CB13
7
220
p
F(CH)
CB13
7
220
p
F(CH)
CP
6
3
CP
6
3
CB13
9
220
p
F(CH)
CB13
9
220
p
F(CH)
CB138
220
p
F(CH)
CB138
220
p
F(CH)
F_SCDR
[0
]_I
AC34
F_SCDR
[1
]_I
AD2
9
F_SCDR
[2
]_I
AD30
F_SCDR
[3
]_I
AD31
F_SCDR
[4
]_I
AD32
F_SCDR
[5
]_I
AD33
F_SCDR
[6
]_I
AD34
F_SCDR
[7
]_I
AE2
9
F_SCDG
[0
]_I
AB32
F_SCDG
[1
]_I
AB33
F_SCDG
[2
]_I
AB34
F_SCDG
[3
]_I
AC2
9
F_SCDG
[4
]_I
AC30
F_SCDG
[5
]_I
AC31
F_SCDG
[6
]_I
AC32
F_SCDG
[7
]_I
AC33
F_SCDB
[0
]_I
Y30
F_SCDB
[1
]_I
AA30
F_SCDB
[2
]_I
AA31
F_SCDB
[3
]_I
AA32
F_SCDB
[4
]_I
AA33
F_SCDB
[5
]_I
AB2
9
F_SCDB
[6
]_I
AB30
F_SCDB
[7
]_I
AB31
F_SCSSYNC_N_I
Y31
F_SCLINGT_I
Y33
F_SCHSYNC_N_I
Y32
F_SCDOTGT_I
Y34
F_CSCANCLK_I
AA2
9
F_CSCANFBCLK_O
AA34
F_HALCLK_I
C2
9
F_SEGCLK_I
B28
F_SYS_REFCLK_I
A2
9
F_DDR_BISTMODE_I
G2
F_DDR_HTMODE_I
F2
F_VPD_I
D3
F_PCI_HTMODE_I
(PD)
B30
F_PCI_HTXRST_I
(PD)
C30
F_PLL_BYPASS
[0
]_I
C31
F_PLL_BYPASS
[1
]_I
B1
F_PLL_BYPASS
[2
]_I
B2
9
F_PLL_MODE_I
A30
F_TCK_I
(PU)
E4
F_TDI_I
(PU)
E2
F_TDO_O
G3
F_TMS_I
(PU)
E3
F_TRST_I
(PU)
E1
F_LSDA
[0
]_O
AL34
F_LSDA
[1
]_O
AM32
F_LSDA
[2
]_O
AM33
F_LSDA
[3
]_O
AM34
F_LSDK
[0
]_O
A
J31
F_LSDK
[1
]_O
A
J32
F_LSDK
[2
]_O
A
J33
F_LSDK
[3
]_O
A
J34
F_LSDK
[4
]_O
AK30
F_LSDK
[5
]_O
AK31
F_LSDK
[6
]_O
AK32
F_LSDK
[7
]_O
AK33
F_LSDC
[0
]_O
AG34
F_LSDC
[1
]_O
AH2
9
F_LSDC
[2
]_O
AH30
F_LSDC
[3
]_O
AH31
F_LSDC
[4
]_O
AH32
F_LSDC
[5
]_O
AH33
F_LSDC
[6
]_O
AH34
F_LSDC
[7
]_O
A
J30
F_LSDM
[0
]_O
AF32
F_LSDM
[1
]_O
AF33
F_LSDM
[2
]_O
AF34
F_LSDM
[3
]_O
AG2
9
F_LSDM
[4
]_O
AG30
F_LSDM
[5
]_O
AG31
F_LSDM
[6
]_O
AG32
F_LSDM
[7
]_O
AG33
F_LSDY
[0
]_O
AE30
F_LSDY
[1
]_O
AE31
F_LSDY
[2
]_O
AE32
F_LSDY
[3
]_O
AE33
F_LSDY
[4
]_O
AE34
F_LSDY
[5
]_O
AF2
9
F_LSDY
[6
]_O
AF30
F_LSDY
[7
]_O
AF31
F_LSCLK_I
AP32
F_LSOUTCLK_O
AP2
9
F_PODCLK_O
AP30
F_LSVSYNCOP_N_O
AN33
F_LSHSYNCOP_N_O
AN34
F_LSVSYNCK_N_I
AM2
9
F_LSVSYNCC_N_I
AL2
9
F_LSVSYNCM_N_I
AN30
F_LSVSYNCY_N_I
AM30
F_LSHSYNCOK_N_O
AL33
F_LSHSYNCOC_N_O
AL32
F_LSHSYNCOM_N_O
AL31
F_LSHSYNCOY_N_O
AK34
F_LSHSYNCK_N_I
AN28
F_LSHSYNCC_N_I
AM28
F_LSHSYNCM_N_I
AL28
F_LSHSYNCY_N_I
AN2
9
JTA
G
MFP
A
SIC
IC2
9
B
SCANNE
RI
/F
LSUI
/F
TE
ST
IC2
9
B
CP5
7
CP5
7
RB80
10
J
RB80
10
J
OE
1
GND
2
OUT
3
VDD
4
X3
X_SG-
9
001LB
X3
X_SG-
9
001LB
CP
7
8
CP
7
8
GP1
7
GP1
7
GP18GP18
CB140
100
p
F(CH)
CB140
100
p
F(CH)
CP
7
5
CP
7
5
CB13
6
220
p
F(CH)
CB13
6
220
p
F(CH)
5
5
4
4
3
3
2
2
D
D
C
C
B
B
A
A
MFPC
P
WB
(MFP
ASIC
SCANN
E
R
/
LSU
)(
M
X-
C
4
01
/M
X-
C38
1,
M
X-
C
4
00
/M
X-
C38
0)
1
8/
4
2
(2
0)
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