MX-C250, MX-C250E, MX-C250F, MX-C250FE, MX-C250FR, MX-C300F, MX-C300W, MX-C300WE, MX-C300A, MX-C300WR (serv.man8). Circuit Diagrams - Sharp Copying Equipment Service Manual (repair manual). Page 15

Read Sharp MX-C250 / MX-C250E / MX-C250F / MX-C250FE / MX-C250FR / MX-C300F / MX-C300W / MX-C300WE / MX-C300A / MX-C300WR (serv.man8) Service Manual online

MX-C300W  CIRCUIT DIAGRAM AND PARTS LAYOUT  2 –  9
5
5
4
4
3
3
D
C
B
A
IPD_RDATA1
IPD_RDATA2
IPD_RDATA0
IPD_RDATA[7..0]
IPD_RDATA3
IPD_RDATA4
IPD_RDATA5
IPD_RDATA6
IPD_GDATA4
IPD_GDATA5
IPD_GDATA6
IPD_GDATA7
IPD_GDATA0
IPD_GDATA1
IPD_GDATA2
IPD_GDATA3
IPD_RDATA7
IPD_GDATA[7..0]
IPD_BDATA1
IPD_BDATA2
IPD_BDATA3
IPD_BDATA4
IPD_BDATA5
IPD_BDATA6
IPD_BDATA7
IPD_BDATA0
IPD_BDATA[7..0]
SBA_SLPZ[12..0]
FPGA_TCK
FPGA_TDO
FPGA_TMS
FPGA_TDI
FPGA_TCK
FPGA_TMS
FPGA_TDI
FPGA_TDO
ZRN_GVDATA0
ZRN_GVDATA[7..0]
ZRN_GVDATA1
ZRN_GVDATA2
ZRN_GVDATA3
ZRN_GVDATA4
ZRN_GVDATA5
ZRN_GVDATA6
ZRN_GVDATA7
SBA_SLPZ0
SBA_SLPZ1
SBA_SLPZ5
SBA_SLPZ6
SBA_SLPZ7
SBA_SLPZ2
SBA_SLPZ8
SBA_SLPZ9
SBA_SLPZ3
SBA_SLPZ4
SBA_SLPZ10
SBA_SLPZ11
SBD_FPGA_SLPZ0
SBD_FPGA_SLPZ[7..0]
SBD_FPGA_SLPZ1
SBD_FPGA_SLPZ2
SBD_FPGA_SLPZ3
SBD_FPGA_SLPZ4
SBD_FPGA_SLPZ5
SBD_FPGA_SLPZ6
SBD_FPGA_SLPZ7
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
3R3VN
DGND
DGND
DGND
DGND
2R5VN
DGND
3R3VN
3R3VN
DGND
DGND
DGND
DGND
DGND
3R3VN
DGND
DGND
3R3VN
DGND
FPGA_PON_nRESET
<3>
IPD_RDATA[7..0]
<16>
IPD_GDATA[7..0]
<16>
IPD_BDATA[7..0]
<16>
SBA_SLPZ[12..0]
<3,16>
IPD_TXCLK
<16>
FPGA_CNFG_DONE
<3>
FPGA_INIT_DONE
<3>
IPD_PS
<16>
IPD_LS
<16>
ZRN_GVDATA[7..0]
<11>
SBRD_SLPZ
<3>
SBWR_SLPZ
<3,16>
SBCS4_SLPZ
<3>
SPI1CS0_LSU_SLPZ
<3>
SPI1CLK_SLPZ
<3,23,26>
SPI1DO_SLPZ
<3,23,26>
SPI1DI_SLPZ
<3>
ZRN_GVPS
<11>
ZRN_GVLS
<11>
GVCLK_SLPZ
<3>
FPGA_NCONFIG
<3>
SBD_FPGA_SLPZ[7..0]
<3,16>
PRIVIDEO1
<12>
PRIVIDEO0
<12>
PRIVIDEO8
<12>
PRIVIDEO9
<12>
PRIVIDEO16
<12>
PRIVIDEO17
<12>
PRIVIDEO24
<12>
PRIVIDEO25
<12>
FPGA_CLK_SLPZ
<3>
XHSYNC_OUT
<11>
XVSYNC_OUT_Y
<11>
XVSYNC_OUT_M
<11>
XVSYNC_OUT_C
<11>
XVSYNC_OUT_K
<11>
ICUCLK_OUT
<11>
C145
0.1u/10v:B
C145
0.1u/10v:B
CP268
CP268
CP274
CP274
CP588
CP588
CP242
CP242
C131
0.1u/10v:B
C131
0.1u/10v:B
C115
0.1u/10v:B
C115
0.1u/10v:B
R933
33J
R933
33J
CP848
CP848
CP247
CP247
C118
0.1u/10v:B
C118
0.1u/10v:B
C126
10u/10v:B(2012)
C126
10u/10v:B(2012)
CP193
CP193
R931
33J
R931
33J
CP272
CP272
C
P
968
C
P
968
CP949
CP949
CP928
CP928
R
108
10KJ
R
108
10KJ
CP258
CP258
C143
10u/10v:B(2012)
C143
10u/10v:B(2012)
R103
51J
R103
51J
CP252
CP252
CP932
CP932
CP840
CP840
CP181
CP181
CP846
CP846
R
102
1KJ
R
102
1KJ
CP243
CP243
CP301
CP301
R
109
10KJ
R
109
10KJ
CP585
CP585
R123
51J
R123
51J
R99
51J
R99
51J
CP217
CP217
CP194
CP194
L12
PZ1608U121-2R0TF(1608)
L12
PZ1608U121-2R0TF(1608)
R929
33J
R929
33J
CP264
CP264
CP245
CP245
CP275
CP275
CP278
CP278
IC20
EP4CE6
IC20
EP4CE6
GNDA1
M5
GNDA2
E12
VCCA1(2.5V)
L5
VCCA2(2.5V)
F12
VCCIO1(3.3V)
G3
VCCIO1(3.3V)
E3
VCCIO2(2.5V)
K3
VCCIO2(2.5V)
M3
VIDEO_IN_A[0](B1IO)
C2
VIDEO_IN_A[1](B1IO)
B1
VIDEO_IN_B[0](B8IO)
C3
VIDEO_IN_B[1](B1IO)
D1
VIDEO_IN_C[0](B1IO)
E5
VIDEO_IN_C[1](B1IO)
D4
VIDEO_IN_D[0](B1IO)
F3
VIDEO_IN_D[1](B1IO)
F5
TDI(TDI:B1IO)
H4
TDO(TDO:B1IO)
J4
TCK(TCK:B1IO)
H3
TMS(TMS:B1IO)
J5
INIT_DONE(INIT_DONE:B6IO)
G16
SPI_CS(B8IO)
A3
SPI_SCK(B8IO)
B3
SPI_SI(B8IO)
C6
SPI_SO(B8IO)
A4
GND
B2
GND
E13
GND
K13
GND
B15
GND
H8
GND
H15
GND
H16
GND
E2
GND
H10
GND
N10
GND
C12
G13
*RSV_IN_WPU(CLK2:B2IO)
M2
SBA[2](B7IO)
C9
SBA[3](B7IO)
D9
SBA[4](B7IO)
E9
SBA[5](B7IO)
F9
SBA[6](B7IO)
A10
SBA[7](B7IO)
B10
SBA[8](B7IO)
E10
SBA[9](B7IO)
F10
SBA[10](B7IO)
A11
SBA[11](B7IO)
B11
*RSV_IN_WPU(B7IO)
D11
SBD[0](B8IO)
B7
SBD[1](B8IO)
E7
SBD[2](B8IO)
F7
SBD[3](B8IO)
F6
SBD[4](B8IO)
E6
SBD[5](B8IO)
D6
SBD[6](B8IO)
B6
SBD[7](B8IO)
A6
SBRD(B8IO)
A7
SBWR(B8IO)
A8
GND+
(CLK5:B6IO)
E16
GND+
(CLK4:B6IO)
E15
VCCIO3(3.3V)
P7
VCCIO3(3.3V)
T1
VCCIO3(3.3V)
P4
VCCIO4(3.3V)
P10
VCCIO4(3.3V)
P13
VCCIO4(3.3V)
T16
VCCIO5(3.3V)
K14
VCCIO5(3.3V)
M14
IPD_GDATA[5](B4IO)
M11
IPD_BDATA[4](B4IO)
N9
IPD_GDATA[3](B4IO)
N11
GVPS(B5IO)
J13
IPD_BDATA[1](B4IO)
M10
IPD_GDATA[7](B4IO)
K10
IPD_RDATA[2](B4IO)
T13
IPD_BDATA[3](B4IO)
P9
IPD_RDATA[7](B4IO)
T15
IPD_RDATA[1](B4IO)
R12
IPD_RDATA[0](B4IO)
T12
IPD_BDATA[6](B4IO)
L9
IPD_RDATA[3](B4IO)
R13
GVCLK(CLK6:B5IO)
M15
IPD_RDATA[5](B4IO)
R14
IPD_GDATA[1](B4IO)
R11
IPD_GDATA[4](B4IO)
N12
IPD_GDATA[0](B4IO)
T11
IPD_BDATA[5](B4IO)
M9
IPD_BDATA[2](B4IO)
L10
IPD_GDATA[6](B4IO)
L11
IPD_PS(B4IO)
T10
IPD_BDATA[0](B4IO)
R10
IPD_RDATA[6](B4IO)
P14
IPD_GDATA[2](B4IO)
P11
IPD_BDATA[7](B4IO)
K9
IPD_TXCLK(B4IO)
T9
IPD_LS(B4IO)
R9
IPD_RDATA[4](B4IO)
T14
PON_nRESET(B7IO)
A15
GND+(CLK3:B2IO)
M1
CONF_DONE(CONF_DONE:B6IO)
H14
nSTATUS(nSTATUS:B1IO)
F4
nCONFIG(nCONFIG:B1IO)
H5
nCE(nCE:B1IO)
J3
GVLS(B5IO)
J11
GVDATA[0](B5IO)
L13
GVDATA[1](B5IO)
M12
GVDATA[2](B5IO)
R16
GVDATA[3](B5IO)
P15
GVDATA[4](B5IO)
P16
GVDATA[5](B5IO)
L14
GVDATA[6](B5IO)
N13
GVDATA[7](B5IO)
N14
SBCS4(B7IO)
D14
SBA[0](B7IO)
A14
SBA[1](B7IO)
C11
*RSV_IN_WPU(B2IO)
L3
*RSV_IN_WPU(B2IO)
J6
*RSV_IN_WPU(B2IO)
P2
*RSV_IN_WPU(B2IO)
L4
*RSV_IN_WPU(B5IO)
J14
XHSYNC_OUT(B1IO)
G2
XVSYNC_OUT_C(B1IO)
G1
ICUCLK_OUT(B3IO)
R4
XVSYNC_OUT_K(B1IO)
G5
CPUCLK(CLK7:B5IO)
M16
XVSYNC_OUT_Y(B7IO)
B13
XVSYNC_OUT_M(B7IO)
C14
C151
0.1u/10v:B
C151
0.1u/10v:B
R927
33J
R927
33J
CP266
CP266
C116
0.1u/10v:B
C116
0.1u/10v:B
C153
0.1u/10v:B
C153
0.1u/10v:B
CP279
CP279
C149
0.1u/10v:B
C149
0.1u/10v:B
C129
0.01u/25v:B
C129
0.01u/25v:B
CP910
CP910
CP280
CP280
C117
0.1u/10v:B
C117
0.1u/10v:B
C146
0.1u/10v:B
C146
0.1u/10v:B
CP291
CP291
CP289
CP289
C150
0.1u/10v:B
C150
0.1u/10v:B
C141
0.01u/25v:B
C141
0.01u/25v:B
R
106
10KJ
R
106
10KJ
JTAG-CN
CN3
BM08B-SRSS-TB(LF)(SN)
JTAG-CN
CN3
BM08B-SRSS-TB(LF)(SN)
DC+3.3V
1
N.C
2
TMS
3
TCK
4
TRST
5
TDI
6
TDO
7
DGND
8
R970
33J
R970
33J
C152
0.1u/10v:B
C152
0.1u/10v:B
CP930
CP930
R116
0J
R116
0J
C147
0.1u/10v:B
C147
0.1u/10v:B
CP933
CP933
CP262
CP262
R932
33J
R932
33J
C144
0.1u/10v:B
C144
0.1u/10v:B
CP294
CP294
CP260
CP260
R930
33J
R930
33J
CP299
CP299
CP270
CP270
CP586
CP586
C128
0.1u/10v:B
C128
0.1u/10v:B
R
100
10KJ
R
100
10KJ
R
101
10KJ
R
101
10KJ
C612
100p/50v:CH
C612
100p/50v:CH
CP263
CP263
R
107
10KJ
R
107
10KJ
C130
1000p/50v:B
C130
1000p/50v:B
CP256
CP256
CP906
CP906
BR41
100Jx4
BR41
100Jx4
8
1
7
2
6
3
5
4
CP843
CP843
CP187
CP187
CP911
CP911
C142
1000p/50v:B
C142
1000p/50v:B
CP287
CP287
CP273
CP273
CP116
CP116
CP295
CP295
CP931
CP931
R928
33J
R928
33J
CP947
CP947
CP283
CP283
CP281
CP281
CP276
CP276
CP285
CP285
CP250
CP250
C148
0.1u/10v:B
C148
0.1u/10v:B
R926
33J
R926
33J
CP297
CP297
C127
1u/10v:B(1608)
C127
1u/10v:B(1608)
R96
33J
R96
33J
CP945
CP945
CP254
CP254
CP584
CP584
DDRIISDRAM  Interface(On Board Only)
Display
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