Read Sharp MX-6201N / MX-7001N (serv.man45) Service Manual online
MX-7001N CIRCUIT DIAGRAM / 回路図 2 – 6
SA_VCCNG_3
.3V
DGND
DGND
+
3
.3V
DGND
+
3
.3V
DGND
+
3
.3V
DGND
+
3
.3V
DGND
DGND
+
3
.3V
DGND
DGND
DGND
DGND
+
3
.3V
+
3
.3V
DGND
+
5V_IN
+
3
.3V
DGND
DGND
DGND
+
3
.3V
DGND
DGND
DGND
+
3
.3V
DGND
+
3
.3V
SRAM_CE2_BASE
{18
,51
}
GPO_SELFRST
{43
}
RES_MFP_MT
{31
}
RES_MFP_FAX2
{2
9}
nIFASIC_RST_BASE
{18
}
JTAGICE_RESET
{7}
V33_RTN_JIG1
{2
0}
CPU_MODECLK_2
.5V
{7}
CPU_MODECLK_3
.3V
{2
0}
GPO_nSOFTRST_PCI2
{43
}
GPO_nSOFTRST_IMG
{43
}
GPO_nSOFTRST_PCI1
{43
}
nPCI1_RST
{1
7,
23
,33
}
nPCI2_RST
{1
6,
3
6,
4
7}
nIMGASIC_RST
{4
0,
42
}
SA_VCCOK_2
.5V
{7,
8
}
nIOGA_RST
{43
,51
}
SA_CPURST_2
.5V
{7,
8
}
RESET_GOOD
{2
0}
nSYSTEM_RST
{13
}
SRAM_CE2_DELAY
{51
}
nFROM_RST
{25
,2
6}
SELF_RESET
b
y
MPU
Force
Reset
by
Anot
h
er
PWB
CP1
07
R1
09
1
00
J
CP
9
4
CP
97
CP
90
C4
0.
1uF(B)
CP112
5
6
14
7
IC1
6
C
SN
7
4LVC14APWR
E
B
C
Q
7
DTC114YUA
1
0
K
4
7
K
CP
9
1
CP
9
1
E
B
C
1
0
K
4
7
K
Q
8
DTC114YUA
11
1
0
14
7
IC1
6
E
SN
7
4LVC14APWR
8
1
7
2
6
3
5
4
BR3
1
0
KJ
x4
C
60
0.
1uF(B)
C5
X_1
000
pF
CP1
00
R1
06
1
0
KJ
8
1
7
2
6
3
5
4
BR4
4
7
KJ
x4
E
B
C
1
0
K
4
7
K
Q
6
DTC114YUA
CP1
0
4
C52
0.
1uF(B)
9
8
14
7
IC1
6
D
SN
7
4LVC14APWR
CP1
0
5
CP115
R142
33J
CP
9
2
CP11
0
CP111
CP
9
5
C5
7
1
000
pF
CP
9
8
R111
1KJ
3
4
14
7
IC1
6
B
SN
7
4LVC14APWR
CP1
09
NC
1
A
2
GND
3
Y
4
VCC
5
IC11
SN
7
4LVC1G
0
4DCK
Y=/A
C
7
4
0
1uF(1
60
8:B)
CP1
0
8
CP1
0
3
CP1
06
CP
96
13
12
14
7
IC1
6
F
SN
7
4LVC14APWR
R113
1
0
KJ
R113
1
0
KJ
E
B
C
1
0
K
4
7
K
Q
9
DTC114YUA
CP1
0
2
CP1
0
1
CP
99
R1
07
33J
R1
07
33J
CP114CP114
GND
1
VDD
2
CT
3
VOUT
4
IC15
BU4242F
CP
9
3
E
B
C
Q
5
DTC114YUA
1
0
K
4
7
K
CP113
1
2
14
7
IC1
6
A
SN
7
4LVC14APWR
C5
9
0.
1uF(B)
1A1
2
1A2
4
1A3
6
1A4
8
2A1
11
2A2
13
2A3
15
2A4
1
7
1G
1
2G
1
9
1Y1
18
1Y2
1
6
1Y3
14
1Y4
12
2Y1
9
2Y2
7
2Y3
5
2Y4
3
VCC
2
0
GND
1
0
IC18
SN
7
4LVC244APWR
C
6
2
0.
1uF(B)
C55
0.
1uF(1
60
8:B)
5
5
4
4
43
32
2
1
1
D
D
C
C
B
B
A
A
MFPC
PWB
(R
eSet
Tree
)
4/52
(6
)
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