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MX-5111 BLOCK DIAGRAM / ブ ロ ッ ク 図
1 – 8
7. SERIAL COMMUNICATION / シ リ アル通信
O.
C
RB_TxD_SCN
UA
R
T
B
_
T
X
D
6
Schmit
In
v.
RB_RxD_SCN
U
A
R
T
B_RXD6
O.
C
RB_R
TS_SCN
U
A
R
T
B_R
TS_N6
Schmit
In
v.
RB_CTS_SCN
U
A
R
T
B_CTS_N6
Schmit
In
v.
O.
C
Schmit
In
v.
O.
C
I/O
ASIC
µPD658
92GC
RxD
TxD
A[4:0]
D[15:8]
CPU
R
T
S_DSPF
CTS_DSPF
H8S/2373
RxD
RxD_DSPF
Schmit
In
v.
TxD
TxD_DSPF
O.
C
O.
C
SCN
Cnt
Schmit
In
v.
Schmit
In
v.
O.
C
RxD
TxD
I/O
I/O
CPU
H8S/2373
DSPF
Cnt
(f
o
r
D
SPF
model)
CPU
H8S/2373
D[15:8]
A[9
:0]
Schmit
In
v.
RB_RXD_PCU
UA
R
T
B
_
R
X
D
7
O.
C
O.
C
O.
C
O.
C
TxD2
RxD2
O.
C
O.
C
O.
C
O.
C
O.
C
O.
C
O.
C
O.
C
TxD3
RxD3
TxD4
RxD4
O.
C
O.
C
/PCU_RxD
O.
C
TxD0
TRANS_D
A
T
Schmit
In
v.
TxD1
RSV_D
A
T
Schmit
In
v.
RxD1
SCK
O.
C
SCL1
Mother
RxD
TxD
I/O
I/O
Schmit
In
v.
Schmit
In
v.
O.
C
O.
C
RxD
TxD
I/O
I/O
O.
C
O.
C
O.
C
O.
C
CPU
M30843
RxD
TxD
I/O
I/O
O.
C
O.
C
O.
C
O.
C
I/O
O.
C
I/O
O.
C
H8S/3684
CPU
H8S/3687
CPU
DESK
FINISHER
(Optional)
(Optional)
(Optional)
LCC
PCU
UPD65
9
46GN-178
PMC
A
SIC
IO
ASIC
LZ
9
A82805GN
/TXD_INS
/RxD_INS
DTR_INS
DSR_INS
/TxD_LCC
/RxD_LCC
/DTR_LCC
/DSR_LCC
/TxD_DSK
/RxD_DSK
/DTR_DSK
/DSR_DSK
TRC_DSK
TRC_LCC
Buff
er
Buff
er
O.
C
Schmit
In
v.
Schmit
In
v.
O.
C
RB_TXD_PCU
UA
R
T
B
_
T
X
D
7
Schmit
In
v.
RB_CTS_PCU
U
A
R
T
B_CTS_N7
O.
C
RB_R
TS_PCU
U
A
R
T
B_R
TS_N7
/PCU_TxD
Schmit
In
v.
RxD0
/PCU_DSR
O.
C
I/O
por
t
/PCU_DTR
Schmit
In
v.
I/O
por
t
O.
C
RC_TxD_PIC
U
A
R
T
C_TXD
Schmit
In
v.
PIC
O.
C
Schmit
In
v.
RC_RxD_PIC
U
A
R
T
C_RXD
O.
C
RC_CLR_PIC
POR
T
C15
O.
C
O.
C
Schmit
In
v.
RC_REQ_PIC
POR
T
C16
LVDS
RB_TXD_F
AX1D
RB_RXD_F
AX1D
RB_TXD_F
A
X1CS
RB_RXD_F
AX1CS
UA
R
T
B
_
T
X
D
0
U
A
R
T
B_RXD0
UA
R
T
B
_
T
X
D
3
UA
R
T
B
_
R
X
D
3
244
244
244
244
ASIC
Ne
w
CPU
SH7706
PIC
TxD
RxD
1st
F
A
X
(f
or
F
Model)
RB_R
TS_F
AX1D
RB_CTS_F
AX1D
RB_R
TS_F
AX1CS
RB_CTS_F
AX1CS
U
A
R
T
B_R
T
S0
UA
R
T
B
_
C
T
S
0
U
A
R
T
B_R
T
S3
UA
R
T
B
_
C
T
S
3
Schmit
In
v.
O.
C
244
Schmit
In
v.
O.
C
244
O.
C
O.
C
Schmit
In
v.
Schmit
In
v.
O.
C
O.
C
Schmit
In
v.
Schmit
In
v.
TxD_F
AX(D)-
TxD_F
AX(D)+
RxD_F
AX(D)+
RxD_F
AX(D)-
TxD_F
AX(CS)-
TxD_F
AX(CS)+
RxD_F
AX(CS)-
RxD_F
AX(CS)+
RB_TXD_F
AX2D
U
A
R
TB_TXD1
RB_RXD_F
AX2D
U
A
R
T
B_RXD1
RB_TXD_F
A
X2CS
U
A
R
TB_TXD4
RB_RXD_F
AX2CS
U
A
R
TB_RXD4
LV
D
S
Schmit
In
v.
O.
C
Schmit
In
v.
O.
C
RB_R
TS_F
AX2D
RB_CTS_F
AX2D
RB_R
TS_F
AX2CS
RB_CTS_F
AX2CS
U
A
R
T
B_R
TS1
U
A
R
T
B_CTS1
U
A
R
T
B_R
TS4
U
A
R
T
B_CTS4
RB_TXD_F
AX3D
LV
D
S
U
A
R
TB_TXD2
RB_RXD_F
AX3D
U
A
R
TB_RXD2
RB_TXD_F
A
X3CS
U
A
R
TB_TXD5
RB_RXD_F
AX3CS
U
A
R
TB_RXD5
Schmit
In
v.
O.
C
Schmit
In
v.
O.
C
RB_R
TS_F
AX3D
RB_CTS_F
AX3D
RB_R
TS_F
AX3CS
RB_CTS_F
AX3CS
U
A
R
T
B_R
TS2
U
A
R
T
B_CTS2
U
A
R
T
B_R
TS5
UA
R
T
B
_
C
T
S
5
Optional
2nd
F
A
X
(Same
as
1st
F
AX)
Optional
(Same
as
1st
F
AX)
3rd
F
A
X
POR
T
B11
RB_GPI_CTS_PCI
POR
T
B12
RB_GPO_R
TS_PCI
UA
R
T
B
_
T
X
D
8
RB_TXD_PCI
UA
R
T
B
_
R
X
D
8
RB_RXD_PCI
UA
R
T
B
_
T
X
D
8
UA
R
T
B
_
R
X
D
8
Optional
PCI
SUB
RB_DTR_PCI
RB_DSR_PCI
RB_CTS_RIC
RB_R
TS_RIC
RB_TXD_RIC
RB_RXD_RIC
RB_DTR_RIC
RB_DSR_RIC
U
A
R
T
_CTS_N10
U
A
R
T
_R
TS_N10
UA
R
T
B
_
T
X
D
1
0
U
A
R
T
B_RXD10
POR
T
B3
POR
T
B4
RS232C
Dr
iv
er
RS232C
Dr
iv
er
Optional
Coin
V
ender/PCI
REUS
ASIC
MPFC
Mother
MFPC
RxD
Schmit
In
v.
TxD
Schmit
In
v.
SCK
Schmit
In
v.
LSU
A
SIC
×2(KC/MY)
LSU
Schmit
In
v.
Schmit
In
v.
Schmit
In
v.
Schmit
In
v.
Schmit
In
v.
Schmit
In
v.
Schmit
In
v.
Schmit
In
v.
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