Read Sharp MX-4100N / MX-4101N / MX-5000N / MX-5001N (serv.man6) Service Manual online
MX-4101N BLOCK DIAGRAM / ブロック図 1 – 7
6. SERIAL COMMUNICATION / シリアル通信
CPU
H
8
S/23
7
3
T
xD_DSK
R
xD_DSK
T
xD_FIN
R
xD_FIN
O
.C
.
O
.C
.
O
.C
.
O
.C
.
O
.C
.
O
.C
.
I/O
ASIC
µPD
6
5
8
9
2GC-
103
O
.C
.
O
.C
.
O
.C
.
O
.C
.
O
.C
.
O
.C
.
CPU
M30
8
43FWGP
Sc
hmi
t
In
v.
O
.C
.
O
.C
.
O
.C
.
O
.C
.
O
.C
.
CPU
H
8
/3
6
8
4
CPU
H
8
/3
6
8
7
DTR_FIN
DSR_FIN
DTR_DSK
DSR_DSK
DTR_LCC
T
xD_LCC
R
xD_LCC
DSR_LCC
PCU
FINISHER
(Optional)
DESK
(Optional)
LCC
(Optional)
)
Sc
hmi
t
In
v.
O
.C
.
O
.C
.
O
.C
.
O
.C
.
O
.C
.
A
[4:
0]
D
[15:
8]
Sc
hmi
t
In
v.
Sc
hmi
t
In
v.
Sc
hmi
t
In
v.
SCK_LSU
RSV_DAT
TRANS_DAT
Sc
hmi
t
In
v.
Sc
hmi
t
In
v.
Sc
hmi
t
In
v.
LSU
ASIC
O
.C
.
nPCU_R
xD
Sc
hmi
t
In
v.
nPCU_T
xD
O
.C
.
PCU_DSR
Sc
hmi
t
In
v.
PCU_DTR
Sc
hmi
t
In
v.
O
.C
.
Sc
hmi
t
In
v.
O
.C
.
MFPC
I/F
ASIC
O
.C
O
.C
.
Sc
hmi
t
In
v.
O
.C
.
nT
xD_
SC
N
nR
xD_
SC
N
R
T
S
_S
C
N
CPU
H
8S/23
73
Sc
hmi
t
In
v.
Sc
hmi
t
In
v.
O
.C
Sc
hmi
t
In
v.
CT
S
_S
C
N
Sc
hmi
t
T
xD0
Sc
hmi
t
O
.C
.
O
.C
Sc
hmi
t
In
v.
Sc
hmi
t
In
v.
O
.C
.
O
.C
.
TxD_SCAN
RxD_SCAN
I/O
ASIC
µPD
6
5
8
9
2GC
O
.C
O
.C
.
Sc
hmi
t
In
v.
O
.C
.
DTR_FAX
(D)
DSR_FAX
(D)
DTR_FAX
(CS)
Sc
hmi
t
In
v.
Sc
hmi
t
In
v.
O
.C
Sc
hmi
t
In
v.
DSR_FAX
(CS)
P
.D
.
P
.U
.
P
.D
.
P
.U
.
P
.D
.
P
.U
.
P
.U
.
P
.D
.
P
.D
.
P
.U
.
P
.U
.
P
.U
.
P
.U
.
P
.U
.
P
.U
.
P
.U
.
P
.U
.
P
.U
.
P
.U
.
P
.U
.
P
.U
.
P
.U
.
P
.U
.
P
.U
.
P
.U
.
P
.U
.
P
.U
.
P
.U
.
P
.U
.
P
.U
.
P
.U
.
P
.U
.
P
.U
.
P
.U
.
P
.U
.
P
.U
.
P
.U
.
P
.U
.
P
.U
.
P
.U
.
P
.U
.
P
.U
.
P
.D
.
P
.D
.
P
.U
.
P
.U
.
P
.D
.
P
.U
.
P
.U
.
P
.U
.
P
.D
.
P
.D
.
P
.U
.
P
.D
.
P.D
.
P.U
.
P.U
.
P.D
.
P.U
.
P.D
.
P.U
.
P.D
.
A
[4:
0]
D
[15:
8]
P
.D
.
P
.U
.
P
.U
.
P
.D
.
P
.D
.
P
.U
.
P
.U
.
P
.D
.
T
xD_FAX
(D)
R
xD_FAX
(D)
T
xD_FAX
(CS)
R
xD_FAX
(CS)
LVD
S
R
xD
0
I/O
port
I/O
port
T
xD1
R
xD1
SC
K1
T
xD2
R
xD2
T
xD3
R
xD3
T
xD4
R
xD4
R
xD
T
xD
SCK
R
xD
T
xD
I/O
I/O
R
xD
T
xD
I/O
I/O
R
xD
T
xD
I/O
I/O
R
xD
[1
]
T
xD
[1
]
CT
S
[1
]
RT
S
[1
]
R
xD
[2
]
T
xD
[2
]
CT
S
[2
]
RT
S
[2
]
R
xD
[3
]
T
xD
[3
]
CT
S
[3
]
RT
S
[3
]
T
xD
[4
]
R
xD
[4
]
CT
S
[4
]
RT
S
[4
]
PI
C
T
xD
[PI
C
]
R
xD
[PI
C
]
O
.C
.
Sc
hmi
t
In
v.
P
.U
.
P
.D
.
nT
xD_
P
IC
O
.C
Sc
hmi
t
In
v.
nR
xD_
P
IC
P
.U
.
CL
R
[PI
C
]
O
.C
.
O
.C
P
.U
.
CL
R
_PI
C
RE
Q[
PI
C
]
Sc
hmi
t
In
v.
RE
Q
_P
IC
O
.C
P
.U
.
LSU
DSPF
Cnt(
for
DSPF
mod
e
l)
SC
N
C
nt
Mo
the
r
MF
P
C
1st
F
AX
(f
or
FG
Mod
e
l)
RxD
TxD
DS
R
_SC
A
N
DT
R
_S
C
A
N
I/O
I/O
N
ew
AS
IC
T
xD_
FA
X(
D)
+
T
xD_
FA
X(
D)
-
R
xD_
FA
X
(D)
+
R
xD_
FA
X
(D)
-
T
xD_
FA
X
(C
S
)+
T
xD_
FA
X
(C
S
)-
R
xD_
F
A
X(
C
S
)+
R
xD_
F
A
X(
C
S
)-
CP
U
SH
77
06
PI
C
T
xD
R
xD
2nd
F
AX
(sam
e
as
1st)
(Optional)
P
.U
.
.
In
v.
In
v.
CPU
H
8
S/23
7
3
TxD
RxD
R
xD
T
xD
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