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AR-P16 PRINT CONTROL PWB / プリントコントロール PWB 2 - 3
5
5
6
6
7
7
8
8
A
B
C
D
R508
10K
NO ASM
R524
10K
NO ASM
R531
10K
NO ASM
R519
10K
R518
10K
NO ASM
R516
10K
R525
10K
NO ASM
R503
10K
R526
10K
R509
10K
R561
10K
R523
10K
R528
10K
NO ASM
R447
10K
NO ASM
R512
10K
R511
1K
NO ASM
R534
10K
R560
10K
NO ASM
R533
10K
NO ASM
R454
10K
R530
10K
R506
10K
R515
10K
NO ASM
R502
1K
NO ASM
R505
10K
NO ASM
R527
10K
R514
10K
BA[0..1]
MA2
MA5
MA[0..13]
MA9
MA7
MA6
MA8
MA3
MA1
MA4
MA10
BA0
MDL0
VCC-107IO
VCC-107IO
VCC-107IO
VCC-107IO
VCC-107IO
VCC-107IO
VCC-107IO
VCC-107IO
VCC-107IO
VCC-107IO
VCC-107IO
VCC-107IO
VCC-107IO
VCC-107IO
FOEN
7,9
BA[0..1]
7,11
RCS0N
7,9
MA[0..13]
7,11
MDL[0..31]
10,11,12
Boot Memory Location [/RCS0]
0 : Indicates that boot ROM is located on the PCI bus
1 : Indicates that boot ROM is located on local processor/memory data bus
0 MPC107 is a PCI agent device
1 MPC107 is a PCI master (host) device
0 : PCI arbiter enabled
1 : PCI arbiter disabled
[SDMA8, SDMA7]
11 : 8-ohm drive capability
10 : 13.3-ohm drive capability
01 : 20-ohm drive capability
00 : 40-ohm drive capability
0 : High drive capability on PCI signals (25 ohm)
1 : Medium drive capability on PCI signals (50 ohm)
0 : High drive capability on CPU signals (20 ohm)
1 : Medium drive capability on CPU signals (40 ohm)
0 : DLL lock range extended
1 : Standard DLL range
ROM Data Width [MDL(0), FOE]
0 : The MPC107 is configured for address map A
(not supported when operating in PCI agent mode)
1 : The MPC107 is configured for address map B
[SDMA4, SDMA3, '0'] (UM-Section 4.3.2)
000 : Recommended for 66MHz PCI bus
100 : Recommended for 33MHz PCI bus
For ROM/FLASH chip select #0/1
RCS0 RCS1 MDL0 FOE MCCR4-bit17
(bit) (bit)
------------------------------------------------
64 64 1 0 0
64 8 1 0 1
8 64 1 1 0
8 8 1 1 1
[MPC107 RESET CONFIGURATION] (UM-Section 2.4)
Initial Address Map [SDBA0]
MPC107 Host Mode [SDMA10]
PCI Arbiter [SDMA9]
1 : 20-ohm data bus drive capability; when this is selected,
only 8-ohm or 13.3-ohm drive capability is allowed for SDMA7
0 : 40-ohm data bus drive capability; when this is selected,
only 20-ohm or 40-ohm drive capability is allowed for SDMA7
Driver capability for MDH[0:31], MDL[0:31], PAR[0:7], and RCS1 [SDMA8]
Driver capability for address signals (RAS/CS[0:7], CAS/DQM[0:7], WE, FOE, RCS0,
RCS2, RCS3, SDBA0, SDRAS, SDCAS, CKE, AS, SDMA[13:0]) [SDMA7]
Driver capability for PCI and EPIC controller output signals [SDMA6]
Driver capability for SDA, SCL, CKO, QACK, and MCP as well as 60x output signals [SDMA5]
PCI output hold delay value (in nanoseconds) relative to PCI_SYNC_IN [SDMA4, SDMA3]
(Section 2.3.3)
0 : Clock flip enabled
1 : No clock flip
Clock flip disable [SDMA2]
DLL lock range extend [SDMA1]
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