AR-FN1 (serv.man10). ARFN1 Service Manual-Description of Circuits - Sharp Copying Equipment Service Manual (repair manual). Page 4

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3. CPU (HB/3040)
A. Outline
The CPU (IC2) controls finisher loads and the system synchronously,
transmitting and receiving data to and from the copier main PWB
through the serial communication line. 
B. Features
The HB/3040 is a high-performance single chip microprocessor using
the 32-bit H8/300H CPU as a core, integrating peripheral functions
necessary for system configuration. 
The HB/300H CPU has an internal 32-bit configuration and is
equipped with 16-bit 
×
 16 general-purpose registers and a simple,
optimized instruction set for high-speed operation. It can handle 16M
byte linear address space.
As peripheral functions, it contains ROM, RAM, 16-bit integrated
timer unit (ITU), programmable timing patter controller (TPC), watch-
dog timer (WDT), serial communication interface (SCI), A/D con-
verter, D/A converter, I/O port, DMA controller (DMAC), and refresh
controller. 
C. Terminal connection diagram
Vcc
TIOCA3/TP8/PB0
TIOCB3/TP9/PB1
TIOCA4/TP10/PB2
TIOCB4/TP11/PB3
TOCXA4/TP12/PB4
TOCXB4/TP13/PB5
DREQ0/
T
P1
4/
PB6
ADTRG/
DREQ1/TP15/PB7
RES0
Vss
TXD0/
P90
TXD1/
P91
R
X
D
0/P92
R
X
D
1/P93
IR
Q4
/SCK0
/P94
IR
Q5
/SCK1
/P95
D
0/P4
0
D
1/P4
1
D
2/P4
2
D
3/P4
3
Vss
D
4/P4
4
D
5/P4
5
D
6/P4
6
A Vcc
  Vref
P70/AN0
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P76/AN6/DA0
P77/AN7/DA1
A Vss
P80/RFSH/IRQ0
P81/CS3/RAS/IRQ1
P82/CS2/IRQ2
P83/CS1/IRQ3
P84/CS0
Vss
PA0/TP0/TEND0/TCLKA
PA1/TP1/TEND1/TCLKB
PA2/TP2/TIOCA0/TCLKC
PA3/TP3/TIOCB0/TCLKD
PA4/TP4/TIOCA1/A23
PA5/TP5/TIOCB1/A22
PA6/TP6/TIOCA2/A21
PA7/TP7/TIOCB2/A20
H8/3040
MD2
MD1
MD0
P66
/LW
R
P6
5/
HWR
P6
4/
RD
P63/AS
Vcc
XTAL
EXTAL
Vss
NMI
RES
STBY
Φ
P62/BACK
P61/BREQ
P60/WAIT
Vss
P53/A19
P52/A18
P51/A17
P50/A16
P27/A15
P26/A14
A13/P25
A12/P24
A11/P23
A10/P22
A9/P21
A8/P20
Vss
A7/P17
A6/P16
A5/P15
A4/P14
A3/P13
A2/P12
A1/P11
A0/P10
35   Vcc
D15/P37
D14/P36
D13/P35
D12/P34
D11/P33
D10/P32
D9/P31
D8/P30
D7/P47
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