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AR-CF2 ELECTRICAL SECTION 9 - 7
(4) Flapper Solenoid and Registration Clutch Drive Circuit (F_SOL and R_CL)
This circuit controls the flapper solenoid operation and the registration
clutch engagement.
clutch engagement.
When the signal F_SOL is "H", Q2 turns on to activate the solenoid.
Similarly, when the signal R_CL is "H", Q3 turns on to engage the
clutch.
Similarly, when the signal R_CL is "H", Q3 turns on to engage the
clutch.
The flapper solenoid drive signal is the PWM signal. At the beginning
of the solenoid activation, the signal is adjusted to set the solenoid at
100% duty cycle. After the plunger of the solenoid is pulled in, the sig-
nal is adjusted to set the solenoid at 70% duty cycle in order to reduce
the temperature rise with the plunger hold.
of the solenoid activation, the signal is adjusted to set the solenoid at
100% duty cycle. After the plunger of the solenoid is pulled in, the sig-
nal is adjusted to set the solenoid at 70% duty cycle in order to reduce
the temperature rise with the plunger hold.
(5) Reset Circuit
The circuit transmits a reset signal to the CPU when the power is
turned on or a power brownout is detected.
turned on or a power brownout is detected.
The circuit includes a watchdog timer intended to the CPU system
operation diagnosis.
operation diagnosis.
After the power is turned on, normally IC3-Pin8 (*RES) is "H". How-
ever, when the +5V voltage falls to 4.2V or less because of the power
turned off or any trouble, IC3-Pin8 turns "L" to reset the CPU.
ever, when the +5V voltage falls to 4.2V or less because of the power
turned off or any trouble, IC3-Pin8 turns "L" to reset the CPU.
The clock signal from the CPU is transmitted to IC3-Pin3 (CK) at a reg-
ular interval to clear the watchdog timer embedded in IC3. However, if
the clock signal from the CPU disappears because of a system trouble,
IC3-Pin8 turns "L" to reset the CPU and stop the system operation.
ular interval to clear the watchdog timer embedded in IC3. However, if
the clock signal from the CPU disappears because of a system trouble,
IC3-Pin8 turns "L" to reset the CPU and stop the system operation.
(6) EEPROM Circuit
This circuit consists of the data storage EEPROM and the peripheral
circuits.
circuits.
IC4 is a storage memory for the adjustment settings of the reverse sen-
sor (reflective sensor) and the paper width detection potentiometer,
and passes the data to the CPU through the four-wire serial interface.
sor (reflective sensor) and the paper width detection potentiometer,
and passes the data to the CPU through the four-wire serial interface.
Once data is stored, the data is retained and not cleared even if the
power is turned off.
power is turned off.
IC4-Pin1 (CS) is the chip selection terminal, and stays "H" during pass-
ing data.
ing data.
IC4-Pin2 (SK) is the serial clock terminal. The serial data is transmitted
synchronizing with the clock signal input to the terminal
synchronizing with the clock signal input to the terminal
IC4-Pin3 (DI) is the serial data input terminal. IC4-Pin4 (DO) is the
serial data output terminal.
serial data output terminal.
Registration CL
Flapper SOL
Not Mounted
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