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AM-400DE
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OA-2000 (IC1) Terminal description (4/4)
2.1.2 Memory block
1) LH28F160BJE (IC6): pin-48 TSOP (FLASH MEMORY)
1) LH28F160BJE (IC6): pin-48 TSOP (FLASH MEMORY)
16Mbit FLASH Memory.
Firmware being compressed except for boot program, is stored in this
device. All of the entry data, user setting and so on are also stored.
device. All of the entry data, user setting and so on are also stored.
2) W9812G6DH-75 or IS42S16800A-7TL (IC4): pin-54 TSOP
(SDRAM)
(SDRAM)
128Mbit (2M x 16bit x 4bank) Synchronous DRAM.
On power on sequence, the firmware being compressed and stored in
FLASH memory (IC6) is decompressed to this device. After decom-
pression, this device is used as a program execution memory. It is also
used as various work memories and communication buffer etc.
FLASH memory (IC6) is decompressed to this device. After decom-
pression, this device is used as a program execution memory. It is also
used as various work memories and communication buffer etc.
2.1.3 MODEM block
1) MODEM
1) MODEM
The block is mainly composed of the G3 FAX modem FM336PLus
(IC18), and is provided with the following modem function.
(IC18), and is provided with the following modem function.
1) G3 FAX modem
The modem satisfies the requirements specified in ITU-T recom-
mendations V.34 half-duplex, V.17, V.33, V.29, V.27 ter, V.21, and
meets the binary signaling requirements of V.8 and T.30 with Annex
F. Internal HDLC support eliminates the need for an external serial
input/output (SIO) device in the DTE for products incorporating
error detection and T.30 protocol. The modem can perform HDLC
framing per T.30 at all data speeds. CRC generation/checking
along with zero insertion/deletion enhances SDLC/HDLC frame
operations. Two FSK (V.21 Ch. 1 and V.21 Ch. 2) flag pattern
detectors facilitate FSK detection during high-speed reception. The
modem features a programmable DTMF transmitter/receiver and
three programmable tone detectors.
mendations V.34 half-duplex, V.17, V.33, V.29, V.27 ter, V.21, and
meets the binary signaling requirements of V.8 and T.30 with Annex
F. Internal HDLC support eliminates the need for an external serial
input/output (SIO) device in the DTE for products incorporating
error detection and T.30 protocol. The modem can perform HDLC
framing per T.30 at all data speeds. CRC generation/checking
along with zero insertion/deletion enhances SDLC/HDLC frame
operations. Two FSK (V.21 Ch. 1 and V.21 Ch. 2) flag pattern
detectors facilitate FSK detection during high-speed reception. The
modem features a programmable DTMF transmitter/receiver and
three programmable tone detectors.
2) Features
• 2-wire half-duplex fax modem modes with send and receive
data rates up to 33.6 kbps.
- V.34 half-duplex, V.17, V.33, V.29, V.27 ter, and V.21 Channel
2
2
- Short train option in V.17 and V.27 ter
• 2-wire duplex data modem modes
- V.21, V.23 (75 bps TX/1200 bps RX or 1200 bps TX/75 bps
RX)
RX)
• PSTN session starting
- V.8 and V.8 bis signaling
• HDLC support at all speeds
- Flag generation, 0-bit stuffing, ITU-T CRC-16 or CRC-32 cal-
culation and generation
culation and generation
- Flag detection, 0-bit stuffing, ITU-T CRC-16 or CRC-32 check
sum error detection
sum error detection
- FSK flag pattern detection during high-speed receiving
• Tone modes and features
- Programmable single or dual tone generation
- DTMF receiver
- Tone detection with three programmable tone detectors
• Serial and parallel synchronous data
• Automatic Rate Adaptation (ARA) in V.34 half-duplex
• Auto-dial and auto-answer control
• TTL and CMOS compatible DTE interface
- ITU-T V.24 (EIA/TIA-232-E) (data/control)
- Microprocessor bus (data/configuration/control)
• Receive dynamic range:
- 0 dBm to -43 dBm for V.17, V.33, V.29, V.27 ter and V.21
- -9 dBm to -43 dBm for V.34 half-duplex
• Caller ID Demodulation
• Single tone detection in Data Mode
• ADPCM Voice Mode (Conexant Proprietary)
• Programmable RSLD turn-on and turn-off thresholds
• Programmable transmit level: 0 to -15 dBm
• Adjustable speaker output to monitor received signal
• DMA support for interrupt lines
• Two 16-byte FIFO data buffers for burst data transfer with
extension upto 255 bytes
• Diagnostic capability
• V.21 Channel 1 Flag detect and V.21 Channel 2 Flag detect
• +3.3 V operation with +5 V tolerant inputs
• +5 V analog signal interface
• 100-pin PQFP package
• Typical power consumption
- Normal mode: VDD1 = 250 mW (+3.3 V for DSP); VDD = 35
mW (+5 V for IA)
mW (+5 V for IA)
- Sleep mode: VDD1 = 20 mW (+3.3 V for DSP); VDD = 0.1 mW
(+5 V for IA)
(+5 V for IA)
No.
Pin name
I/O
Pin Description
193
DEV_RSDP
Output analog
USB Device Interface
194
DEV_DP
Bidir.analog
USB Device Interface
195
DEV_DM
Bidir.analog
USB Device Interface
196
DEV_AVSS
GND analog
Ground
197
DEV_RREF
Analog
USB Device Reference Input
198
DEV_AVDD33
+3.3V analog
Power
199
DEV_VSENSE
Input
USB Device Interface
200
DEV_RUP
Output
USB Device Interface
201
GP_L0/PO_DATA0
Bidirectional
General Purpose IO/Print Video Data Output
202
GP_L1
Bidirectional
General Purpose IO
203
GP_L2
Bidirectional
General Purpose IO
204
GP_L3
Bidirectional
General Purpose IO
205
GP_L4
Bidirectional
General Purpose IO
206
GP_L5
Bidirectional
General Purpose IO
207
VSS
GND digital
Ground
208
IO_VDD33
+3.3V digital
Power
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