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8
741M -
TOUCH CONTROL ASSEMBLY/DESCRIPTION OF LSI
LSI(IZA918DR)
The I/O signal of the LSI(IZA918DR) are detailed in the following table.
Pin No.
Signal
I/O
Description
1-7
SEG13 -
OUT
Segment data signal.
SEG19
Connected to LCD.
The relation between signals are as follows:
LSI signal (Pin No.)
The relation between signals are as follows:
LSI signal (Pin No.)
LCD
LSI signal (Pin No.) LCD
SEG 13 (1) ..................................... S7
SEG 19 (7) .................................. S1
SEG 14 (2) ..................................... S6
SEG 8 (59) ................................ S12
SEG 15 (3) ..................................... S5
SEG 9 (60) ................................ S11
SEG 16 (4) ..................................... S4
SEG 10 (61) .............................. S10
SEG 17 (5) ..................................... S3
SEG 11 (62) ................................ S9
SEG 18 (6) ..................................... S2
SEG 12 (63) ................................ S8
8
NC
Not connection terminal.
9
NC
Connected to COM2 (LSI Pin No, 49).
10
NC
Connected to COM1 (LSI Pin No, 48).
11
NC
Connected to COM0 (LSI Pin No, 47).
12-13
NC
No connection terminal.
14-16
VC1-VC3
IN/OUT
Terminal not used.
17
XRESET
IN
Auto clear terminal.
Signal is input to reset the LSI to the initial state when power is supplied. Temporarily
set "L" level the moment power is supplied, at this time the LSI is reset. Thereafter
set at "H" level.
set "L" level the moment power is supplied, at this time the LSI is reset. Thereafter
set at "H" level.
18
XTEST
IN
Connected to GND.
19
VSS
IN
Power source voltage: -5V.
Power source voltage is applied to drive the LSI.
20
OSC1
IN
Internal clock oscillation frequency setting input.
The internal clock frequency is set by inserting the ceramic filter oscillation circuit with
respect to OSC2 terminal.
respect to OSC2 terminal.
21
OSC2
OUT
Internal clock oscillation frequency control output.
Output to control oscillation input of OSC1.
22
VD1
IN
Power source voltage input terminal.
Power source voltage is applied to drive the oscillation circuit which makes the clock
signal in the LSI.
signal in the LSI.
23
VDD
IN
Power source voltage: 0V.
Power source voltage is applied to drive the LSI.
24
AVDD
IN
Power source voltage input terminal.
Power source voltage is applied to drive the A/D converter in the LSI. Connected to
GND.
GND.
25
AVREF
IN
Reference voltage input terminal.
A reference voltage is applied to drive the A/D converter in the LSI. Connected to
GND.
GND.
26
AVSS
IN
Power source voltage input terminal.
Power source voltage is applied to drive the A/D converter in the LSI. Connected to
VC. (-5V)
VC. (-5V)
27-28
NC
No connection terminal. (Connected to VC (-5V))
29-32
R40-R43
IN
Terminal to change functions according to the Model.
By using the A/D converter contained in the LSI, DC voltage in accordance with the
Model in operation is applied to set up its function.
Model in operation is applied to set up its function.
33
NC
No connection terminal.
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