Read Sharp ER-A450 (serv.man2) Service Manual online
Pin
No.
SYMBOL
SIGNAL
NAME
IN/
OUT
FUNCTION
33
KR7
KR7
IN
KEY RETURN 7
34
AVRF
GND
35
AVDD
VDD
36
/RESET
/RES0
IN
37
XT2
38
XT1
39
IC
GND
40
X2
41
X1
42
VSS1
GND
43
LDRQ
LDRQ
IN
LORD REQUEST
44
ERC
ERC
IN
EVENT READ CANCEL
45
SHEN
/SHEN
OUT SHIFT ENABLE
46
/RES1
/RESETS
OUT SYSTEM TO RESET
47
ST6
ST6
OUT KEY STROBE 6
48
ST7
ST7
OUT KEY STROBE 7
49
ST8
ST8
OUT KEY STROBE 8
50
ST9
NU
OUT KEY STROBE 9
51
/POFF
/POFF
IN
POWER OFF
52
BUZ
BUZ
OUT BUZZER
53
T0
G1
OUT DISPLAY DIGIT 1
54
T1
G2
OUT DISPLAY DIGIT 2
55
T2
G3
OUT DISPLAY DIGIT 3
56
T3
G4
OUT DISPLAY DIGIT 4
57
T4
G5
OUT DISPLAY DIGIT 5
58
T5
G6
OUT DISPLAY DIGIT 6
59
T6
G7
OUT DISPLAY DIGIT 7
60
T7
G8
OUT DISPLAY DIGIT 8
61
T8
G9
OUT DISPLAY DIGIT 9
62
T9
G10
OUT DISPLAY DIGIT 10
63
T10
NU
OUT DISPLAY DIGIT 11
64
ID
NU
OUT DISPLAY SEGMENT
3. Clock generator
1) CPU (HD64151010FX)
Fig. 3-1
Basic clock is supplied from a 14.7456MHz ceramic oscillator.
The CPU contains an oscillation circuit from which the basic clock is
internally driven. If the CPU was not operating properly, the signal
does not appear on this line in most cases.
The CPU contains an oscillation circuit from which the basic clock is
internally driven. If the CPU was not operating properly, the signal
does not appear on this line in most cases.
2) CKDC8 oscillation circuit
Fig. 3-2
Two oscillators are connected to the CKDC8.
The main clock X3 generates 4.19MHz which is used during power
on.
When power is turned off, the CKDC8 goes into the standby mode
and the main clock stops.
The sub-clock X2 generates 32.768KHz which is primarily used to
update the internal RTC (real time clock). During the standby mode, it
keeps oscillating to update the clock and monitoring the power recov-
ery.
The main clock X3 generates 4.19MHz which is used during power
on.
When power is turned off, the CKDC8 goes into the standby mode
and the main clock stops.
The sub-clock X2 generates 32.768KHz which is primarily used to
update the internal RTC (real time clock). During the standby mode, it
keeps oscillating to update the clock and monitoring the power recov-
ery.
4. Reset (POFF) circuit
Fig. 4-1
In order to prevent memory loss at a time of power off and power
supply failure of the ECR, the power supply condition is monitored at
all times. When a power failure is met, the CPU suspends the execu-
tion of the current program and immediately executes the power-off
program to save the data in the CPU registers in the external S-RAM
with the signal STOP forced low to prepare for the power-off situation.
The signal STOP is supplied to the CKDC8 as signal RESET to reset
the devices.
supply failure of the ECR, the power supply condition is monitored at
all times. When a power failure is met, the CPU suspends the execu-
tion of the current program and immediately executes the power-off
program to save the data in the CPU registers in the external S-RAM
with the signal STOP forced low to prepare for the power-off situation.
The signal STOP is supplied to the CKDC8 as signal RESET to reset
the devices.
CPU
(HD64151010FX)
99
98
XTAL
EXTAL
14.7456MHz
X1
101
PHAI
37
38
33P
HD404728A91FS
C105
CKDC 8
X2
X3
4.19MHz
4.19MHz
X2
32.768KHz
32.768KHz
2
1
3
41
18P
C106
40
X1
XT2
XT1
R164
330K
330K
+
-
/POFF
3
2
1
4
8
B
IC3A
KIA393F
KIA393F
C3
1000P
1000P
D7
1SS133
C208
1µ 50V
1µ 50V
+
ZD2
MTZ5.1A
MTZ5.1A
R14
9.1KG
9.1KG
R13
15KG
15KG
R10
56K
R11
2.7K
2.7K
R9
2.7K
2.7K
R12
8.2KG
8.2KG
+24V
+5V
POFF
CPU
72
IRQ0
89
RESET (FROM CKDC 8)
STOP (TO CKDC 8)
MPCA7
13
48
1
IR
Q0
54
IN
T0
4 – 9
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