ER-A280, ER-A280N, ER-A280F (serv.man5). ER-A280 Service Manual - Sharp ECR Service Manual (repair manual). Page 10

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ER-A280F/A280N (V)
HARDWARE DESCRIPTIONS
4 – 2
3. MAJOR PARTS / OPTIONS
4. LOGIC CIRCUIT DESCRIPTIONS
1)
MPU
The M30622M6P-557FP in the M16C62 series of RENESUS is used.
The general descriptions of the M30622M6P are as shown blow:
M30622M6P-557FP (557 is a MASK code.)
Internal RAM: 4kByte
Internal ROM: 48kByte
Memory space: 1Mbyte 00000h - FFFFFh
Operating frequency: 24MHz
(* The external clock 12MHz is multiplied by 2 by using the PLL fre-
quency synthesizer.)
■ MPU major setting
• Processor operations
The normal operations and the normal program revising in this ECR
are enable in the microprocessor mode.
For servicing including the program ROM change or revising all the
area of the program ROM, the memory expansion mode is used.
For each device connected with the bus, the space set in the 1M byte
mode is controlled together with the MPU ports A19 - A0, RD#, WR#,
and G/A.
•  Bus control setting
The address bus width is set as 20bit.
•  Chip select control setting
The chip select signal is not used.
The chip select of each device is generated by the G/A decode cir-
cuit.
The wait of each chip select terminal is set to accord to the device
speed.
• RDY# signal setting
An external wait is used for access to a low-speed device.
Therefore, the bit (CS3W - CS0W bit) corresponding to the CSR reg-
ister is set to “0” (with wait).
•  Software wait / External wait
In the compact ECR, the following software wait for each external
memory area is set for operations. The operating frequency is
24MHz. The cycle is, therefore, 1BCLK = 41.67ns.
In the compact ECR, an external wait is enabled by the RDY# signal
input with the access limitation of the device and the access speed.
The external wait trigger is made by G/A.
When making an access to the LCD driver, an external wait of 1 -
2BCLK is set because of limitations on the LCD driver operation
specifications.
For the program save area in the OTP ROM model, an external wait
of 1BCLK is set when making an access to the ROM (OTP) area.
*For the LCD, the control signal is separately controlled with the port.
(Shadhing area)---FLASH ROM model
• Bank control
For control of the SRMA and the program RAM, access is enabled to
each area of the RAM and the program ROM by bank control.
For bank control, the RAM/ROM independent bank is set to the regis-
ter in G/A set to 2E040h and 2E041h, and an access is made.
Major parts
Model name
* Clock frequency
CPU
R E N E S A S
M30622M6P-557FP
* 24MHz
(Multiplying 12MHz
by 2)
GATE ARRAY
N E C   C M O S - 9 H D
D65943 
* 24MHz
(BCLK is used.)
PRINTER
EPSON M-T173H
SRAM
8Mbit
ROM
For program
8Mbit FLASH ROM
(TOP BOOT TYPE)
For E/J
-
For FISCAL
-
DISPLAY MAIN
Japan Subcontract
M32A079X
I/F
USB controller
-
-
RS232 driver
Intersil ISL3243E
Power IC
8.5V
generating
L M 2 5 7 4 D W-
ADJR2G
52kHz
5V
generating
SC4525A
500kHz
24V
generating
L M 2 5 7 4 D W-
ADJR2G
52kHz
12.75V
generating
-
3.3V
generating
BA33DD0WHFP
2.8V
generating
R1154N028B-T1-F
For LCD
backlight
TB62752
1MHz
-
-
-
Memory 
space 
Set
software
Device
External 
wait
Total
CS0#
area
3 wait 
(4BCLK)
SRAM
No
4BCLK
3 wait 
(4BCLK)
ROM
(FLASH)
No
4BCLK
CS1#
area
3 wait 
(4BCLK)
FET
No
4BCLK
LCD
When 1BCLK
WRITE
When 2BCLK 
READ
5BCLK *
6BCLK *
G/A
No
4BCLK
CS2#
area
2 wait 
(3BCLK)
SRAM mapping
No
3BCLK
CS3#
area
2 wait 
(3BCLK)
SRAM mapping
No
3BCLK
Display
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