DV-NC55 (serv.man11). Function list - Sharp DVD Service Manual (repair manual)

dv-nc55 (serv.man11) service manual
Model
DV-NC55 (serv.man11)
Pages
24
Size
212.45 KB
Type
PDF
Document
Service Manual
Brand
Device
DVD / Function list
File
dv-nc55-sm11.pdf
Date

Read Sharp DV-NC55 (serv.man11) Service Manual online

58
DV-NC55S/H
DV-NC60H
Pin No. Terminal name
I/O
Operation function
Terminal DC Voltage(TYP.)
Remarks
1
GND
GND terminal.
2
P2TP
I
TE+input (CD)
VrA
3
P2TN
I
TE–input (CD)
VrA
4
LDO2
O
Drive ouput 2
5
MDI2
I
Monitor input 2
6
VrD
O
Digital VREF
Vdd/2 output (1.65V)
7
Vrfil
Filter capacity for reference
8
Vdd
I
Power terminal
3.3V is connected.
9
DPAC
DPD AC combination capacity 1
10
DPBD
DPD AC combination capacity 2
11
DPD1
DPD integral capacity 1
12
DPD2
DPD integral capacity 2
13
SCB
I
Control line (Bit clock)
2.2[V]
14
SCL
I
Control line (Latch signal)
2.2[V]
15
SCD
I
Control line (Sirial Data)
2.2[V]
16
VRCK
I
Reference clock input
2.3[V]
When frequency is increased, the
filters excepting the servo LPF are
shifted to high frequency side.
17
VCKF
Capacity for VRCK time constant
adjustment
18
VccP
Power terminal
19
LVL
O
Servo addition output
VrD/2
20
TEO
O
TE output
VrD
21
FEO
O
FE output
VrD
22
DFTN
I
DPD difect
Low DPD output: Mute
23
VccS
Power terminal (servo)
24
NC
Used in the open state.
25
RPZ
O
RF ripple output 2
VrD
26
RPO
O
RF ripple output 1
VrD/2
27
RPB
RF ripple bottom
28
RPP
RF ripple peak
29
RFOn
O
Equivalent RF output
1.65[V]
DC voltage varies by RFS.
(Differential output)
30
RFOp
O
Equivalent RF output
1.65[V]
DC voltage varies by RFS.
(Differential output)
31
VccR
Power terminal (RF)
32
RFS
I
RF slice level adjustment
33
TEB
I
TE balance
VrD
When TEB is raised, the gain on the
TP side and the delay amount on the
A+C side are increased.
Adjusting range: GND - Vdd
34
FEB
I
FE balance
VrD
When FEB is raised, the gain on the
A+C (FP) side is increased.
Adjusting range: GND - Vdd
35
DPDB
I
Pit depth adjustment
VrD
When DPDB is raised, the delay
amount on the A•B side is increased.
Adjusting range: GND - Vdd
36
Vcc2
Power terminal
37
NC
Used in the open state.
38
NC
Used in the open state.
39
GND2
GND terminal.
40
TCC1
I
Time constant adjustment
41
RFDC
DC feedback capacity
42
VrA
O
Analog VREF
2.1[V]
43
EQB
I
Boost adjustment
VrD
When EQB is raised, the boost increases.
Adjusting range: GND - Vdd
12. IC FUNCTION LIST
12-1. IC301 TA1323F
RF PROCESSOR
59
DV-NC55S/H
DV-NC60H
• Block Diagram
P1TP
P1TN
LDO1
MDI1
EQF
EQB
VrA
RFDC
TCC1
GND2
NC
NC
Vcc2
DPDB
FEB
TEB
RFS
VccR
RFOp
RFOn
RPP
RPB
RPO
RPZ
NC
VccS
DFTN
FEO
TEO
LVL
VccP
VCKF
P1FN
P1FP
LDP1
P1DI
P1CI
P1BI
P1AI
GNDR
LDP2
P2AI
P2BI
P2CI
P2DI
GNDS
P2FP
P2FN
GND
P2TP
P2TN
LDO2
MDI2
V
rD
V
rfil
V
dd
DPAC
DPBD
DPD1
DPD2
SCB
SCL
SCD
V
RCK
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
 1  2  3  4  5  6  7  8  9  10 11 12 13 14 15 16
Time 
constant 
adjustment
RF Ripple
creation
Output
Amp
T-gain
Adjust
sel-PD
sel-PD
sel-PD
Level
detect
F-gain
Adjust
mode-IC
R-gain
Adjust
3Beam-TE
creation
DPD-TE
creation
FE creation
EQ
APC1
APC2
Vref
BUS
sel-RF
sel-FE
sel-TE
sel-DPD
sel-LVL
mode-TE
F-gain
Adjust
DPDB
TEB
FEB
TEB
TCC1
VrA
tcc1 (BUS)
TE-gain
Adjust
FE-gain
Adjust
DC
FB
Pin No. Terminal name
I/O
Operation function
Terminal DC Voltage(TYP.)
Remarks
44
EQF
I
Frequency adjustment
VrD
When EQF is raised, shift to the
high frequency side occurs.
Adjusting range: GND - Vdd
45
MDI1
I
Monitor input 1
46
LDO1
O
Drive output 1
47
P1TN
I
TE–input (DVD)
VrA
48
P1TP
I
TE+input (DVD)
VrA
49
P1FN
I
FE–input (DVD)
VrA
50
P1FP
I
FE+input (DVD)
VrA
51
LDP1
I
APC polarity 1
Positive polarity when this terminal
is connected to Vcc.
52
P1DI
I
D input (DVD)
VrA
53
P1CI
I
C input (DVD)
VrA
54
P1BI
I
B input (DVD)
VrA
55
P1AI
I
A input (DVD)
VrA
56
GNDR
GND terminal (RF)
57
LDP2
I
APC polarity 2
Positive polarity when this terminal
is connected to Vcc.
58
P2AI
I
A input (CD)
VrA
59
P2BI
I
B input (CD)
VrA
60
P2CI
I
C input (CD)
VrA
61
P2DI
I
D input (CD)
VrA
62
GNDS
GND terminal (Servo)
63
P2FP
I
FE+input (CD)
VrA
64
P2FN
I
FE–input (CD)
VrA
60
DV-NC55S/H
DV-NC60H
12-2. IC501 IX1689GE
FLASH MEMORY
Pin No.
Symbol
Type
Name and function
Byte selection address: When the device is in the x8 mode, the low or high order byte is
45
DQ
15
/A
-1
Input
selected. It is not used in the x16 mode.
(If BYTE# is high, DQ
15
/A
-1
 input circuit does not operate.)
25-18, 8-4
A
0
-A
12
Input
Word selection address: Selection of one word of 16k byte block. These addresses are
latched during data wiring operation.
3-1, 48,
A
13
-A
18
Input
Block selection address: Selection of 1/32 erase block. These addresses are latched
16, 17
during data writing, erasing and lock block operation.
29, 31, 33,
Low order byte data input/output: Command user interface writing cycle data and command
35, 38, 40,
DQ
0
-DQ
7
Input/Output input. Various data read memory identifier and status data output Chip nonselection or
42, 44
output disable: Float state
30, 32, 34, 36,
DQ
8
-DQ
14
Input/Output
High order byte data input/output: The function is the same as that of low order byte
39, 41, 43, 45
data input/output. Operative only in x16 mode. x8 mode: Float state DQ
15
/A
-1
 is address.
26
CE#
Input
Chip enable: Device control logic, input buffer, decoder and sense amp. are activated.
Chip becomes active only when CE# is “Low”.
Reset/Power down: If RP# is set to “Low”, the control circuit is initialized when power
is turned on. Hence, the RP#pin is set to “Low”. When power is turned on or off or in
12
RP#
Input
case of fluctuation it is kept at “Low” so as to protect data from noise. When RP# is in
“Low” state, the device is in deep power down state. 480 ns is required to recover
from the deep power down state. If the RP# pin becomes “Low”, the whole chip operation is
interrupted and reset. After recovery the device is set to array read state.
28
OE#
Input
Output enable: When OE# is set to “Low”, data is output from the DQ pin. When OE# is
set to “High”, the DQ pin is set to float state.
Write enable: Command user interface, data Q register and address Q latch access is
11
WR#
Input
controlled. In “Low” state WR# becomes active. At rise edge the address and data are
fetched.
Write protection: Blanking/writing to the boot block area is input of prohibition control.
14
WP#
Input
Blanking to the boot block area and writing actuation can't be executed at the time of
WP#=V
IL
.
Ready/busy: The state of internal write state machine is output. In “Low” state it is
15
RY/BY#
Output
indicated that the write state machine is in operation. If the write state machine waits for
next operation instruction, erase is suspended or it is in deep power down state, the RY/BY#
pin is in float state.
Byte enable: When BYTE# is set to “Low”, the device is set to the x8 mode. At this time
47
BYTE#
Input
the DQ
8
-DQ
15
 pin becomes float state. Address A
-1
 selects high order/low order byte.
When BYTE# is “High”, the device is set to the x16 mode. The A
-1
 input circuit is disabled.
13
Vpp
———
Write/erase power supply: 5.0 
±
 0.5V is applied during writing/erasing.
37
Vcc
———
Device power supply: 5.0 
±
 0.5V
27, 46
GND
———
Ground
9, 10
NC
———
Nonconnection
61
DV-NC55S/H
DV-NC60H
Output
Buffer
Output
Buffer
Input
Buffer
Input
Buffer
ID
Register
DATA 
QUEUE
REGISTER
CSR
ESRs
Data
Comparator
DQ
8-14
DQ
0-7
I/O Logic
OUTPUT MULTIPLEXER
Register
Program Erase
Voltage Switch
BYTE#
CUI
WSM
16-KBYTE
Block 31
16-KBYTE
Block 30
16-KBYTE
Block 1
16-KBYTE
Block 0
CE#
OE#
WR#
RP#
RY/BY#
V
PP
V
CC
GND
Y GATING/SENSING
Y-DECODER
X-DECODER
Input
Buffer
ADDRESS
QUEUE
LATCHES
ADDRESS
COUNTER
A
-1.0~18
• Block Diagram
• Block Diagram
RAS clock
generator
CAS clock
generator
WE clock
generator
Data I/O Bus
Column decoders
Sense amplifiers
Refresh
counter
Address buffers
and predecoders
Row
decoders
Memory
array
OE clock
generator
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
I/O
Buffer
9
Y
0
-Y
8
X
0
-X
8
512
512  16
OE
WE
UCAS
LCAS
RAS
V
CC
V
SS
A0
A1
A7
A8
12-3. IC502 IX1765GE
4M EDO DRAM
Terminal
Terminal name
Function
16-19, 22-26
A
0
-A
8
Address inputs.
14
RAS
Row address strobe.
28
UCAS
Column address strobe/upper byte control.
29
LCAS
Column address strobe/lower byte control.
13
WE
Write enable.
27
OE
Output enable.
2-5, 7-10
DQ
1
-DQ
16
Data inputs/outputs.
31-34, 36-39
1, 6, 20
V
CC
+3.3V power supply.
21, 35, 40
V
SS
0V ground.
11-12, 15, 30
NC
No connection.
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