Read Sharp DV-760H (serv.man3) Service Manual online
DV-700S
DV-760S/H
DV-760S/H
Pin No.
Terminal name
I/O
Operation function
Remarks
88
BUS3
I/O
89
VDD
–
Digital + power terminal.
90
VSS
–
Digital ground terminal.
91
BUCK
I
Microcomputer interface clock input terminal.
Schmidt input
92
/CCE
I
Microcomputer interface chip enable signal input terminal.
Schmidt input
BUS0 to 3 is active in “L” state.
93
TEST4
I
Test terminal.
Pull-up resistor
To be opened usually.
built in.
94
/TEMOD
I
Local test mode selection terminal.
Pull-up resistor
built in.
built in.
95
/RST
I
Reset signal input terminal.
Pull-up resistor
Reset state: “L”
built in.
96
TEST0
I
Test terminal.
Pull-up resistor
To be opened usually.
built in.
97
/HSO
O
Playback speed mode flag output terminal.
98
/UHSO
O
99
EMPH
O
Subcode Q data emphasis flag output terminal.
Emphasis ON: “H” OFF: “L”
Output polarity can be inverted by the command.
Emphasis ON: “H” OFF: “L”
Output polarity can be inverted by the command.
100
LRCK
O
Channel clock (44.1 kHz) output terminal.
L channel “L” R channel: “H”
Output polarity can be inverted by the command.
L channel “L” R channel: “H”
Output polarity can be inverted by the command.
/UHSO
/HSO
Playback speed
H
H
x1 speed playback
H
L
x2 speed playback
L
H
x4 speed playback
L
L
x8 speed playback
• Block Diagram
76
DVDD
77
RO
78
DVSS
79
DVR
80
LO
81
DVDD
82
TEST1
83
TEST2
84
TEST3
85
BUS0
86
BUS1
87
BUS2
88
BUS3
89
VDD
90
VSS
91
BUCK
92
/CCE
93
TEST4
94
/TEMOD
95
/RST
96
TEST0
97
/HSO
98
/UHSO
99
EMPH
100
LRCK
50 DMO
49 FVO
48 FMO
47 TEBC
46 RFGC
45 VREF
44 TRO
43 FOO
42 TEZI
41 TEIN
40 TSIN
39 SBAD
38 FEIN
37 RFRP
36 RFZI
35 RFCT
34 AVDD
33 RFIN
32 SLCO
31 AVSS
30 VCOF
29 VCOREF
28 PVREF
27 LPFO
26 LPFN
1
2
3
4
VSS
BCK
AOUT
5
6
7
8
MBOB
IPF
SBOK
CLCK
9 10 11 12
VDD
VSS
DATA
13
SBSY
14
SPCK
15
SPDA
16
COFS
17
MONIT
18
VDD
19
TESIO0
20
P2VREF
21
SPDO
22
PDOS
23
PDO
24
XMAXS
25
TMAX
SFSY
DOUT
75 74 73 72
XVDD
XO
XI
71 70 69 68
VDD
PXO
PXI
VSS
67 66 65 64
TESIO1
TESIN
/DACT
63
/DMOUT
62
IO3
61
IO2
60
IO1
59
IO0
58
VSS
57
VDD
56
/SHC
55
/SRCH
54
/DFCT
53
/FOON
52
SEL
51
2VREF
/CKSE
XVSS
LPF
1Bit
DAC
ROM
RAM
1Gk RAM
PWM
D/A
A/D
CLV servo
PWM
VCO
PLL TMAX
+
–
–
+
–
–
+
–
–
+
–
–
Clock
genelator
Servo control
Digital
equalizer
Automatic
adjusting circuit
Micon
inter
face
Digital out
Status
Correction
circuit
Sync signal
protection
EFM
demodulation
Data slicer
Subcode
demodulation
circuit
demodulation
circuit
Audio output
circuit
Address circuit
11-21
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