DV-700 (serv.man3). Section 1-11 - Text - Sharp DVD Service Manual (repair manual). Page 46

VA—Analog Positive Supply: Pin 34

Analog positive supply for clock generator. Nominally +3.3 V.

AGND—Analog Supply Ground: Pin 35

Analog ground for clock generator PLL.

VD1, VD2, VD3—Digital Positive Supply: Pins 1, 12, 23

Digital positive supplies. Nominally +2.5 V.

DGND1, DGND2, DGND3—Digital Supply Ground: Pins 2, 13, 24

Digital ground.

FILT1—Phase-Locked Loop Filter: Pin 33

Connects to an external filter for the on-chip phase-locked loop. This pin does not meet Cirrus Logic's ESD tolerance of 2000V

using the human body model. This pin will tolerate ESD of 1000V using the human body model.

FILT2—Phase Locked Loop Filter: Pin 32

Connects to an external filter for the on-chip phase-locked loop. This pin does not meet Cirrus Logic's ESD tolerane of 2000V

using the human body model. This pin will tolerate ESD of 1000V using the human body model.

CLKIN—Master Clock Input: Pin 30

CS493XX clock input. When in internal clock mode (CLKSEL=DGND), this input is connected to the internal Pll from which all internal

clocks

are derived. When in external clock mode (CLKSEL=VD), this input is connected to the DSP clock.

CLKSEL—DSP Clock Select: Pin 31

This pin selects the clock mode of the CS493XX. When CLKSEL is low, CLKIN is connected to the internal PLL from which all internal
clocks are derived. When CLKSEL is high CLKIN is connected to the DSP clock.

DATA7, EMAD7, GPIO7 — Pin8
DATA6, EMAD6, GPIO6 — Pin9
DATA5, EMAD5, GPIO5 — Pin10
DATA4, EMAD4, GPIO4 — Pin11
DATA3, EMAD3, GPIO3 — Pin14
DATA2, EMAD2, GPIO2 — Pin15
DATA1, EMAD1, GPIO1 — Pin16
DATA0, EMAD0, GPIO0 — Pin17

In parallel host mode, these pins provide a bidirectional data bus. If a serial host mode is selected, these pins can provide a multiplexed
address and data bus for connecting an 8-bit external memory. Otherwise, in serial host mode, these pins can act as general-purpose
input or output pins that can be individually configured and controlled by the DSP.

A0, SCCLK—Host Parallel Address Bit Zero or Serial Control Port Clock: Pin 7

In parallel host mode, this pin serves as one of two address input pins used to select one of four parallel registers. In serial host mode,
this pin serves as the serial control clock signal, specifically as the SPI clock input or the I

2

C clock input.

A1, SCDIN—Host Address Bit One or SPI Serial Control Data Input: Pin 6

In parallel host mode, this pin seves as on of two address input pins used to select one of four parallel registers. In SPI serial host mode,
this pin serves as the data input.

RD, R/W, EMOE, GPIO11—Host Parallel Output Enable or Host Parallel R/W or External Memory Output Enable or General Purpose

Input & Output Number 11: Pin 5

In Intel parallel host mode, this pin serves as the active-low data bus enable input. In Motorola parallel host mode, this pin serves as the
read-high/write-low control input signal. In serial host mode, this pin can serve as the external memory active-low data-enable output
signal. Also in serial host mode, this pin can serve as a general purpose input or output bit.

WR, DS, EMWR, GPIO10—Host Write Strobe or Host Data Strobe or External Memory Write Enable or General Purpose Input &

Output Number 10: Pin 4

In Intel parallel host mode, this pin serves as the active-low data-write-input strobe. In Motorola parallel host mode, this pin serves as the
active-low data-strobe-input signal. In serial host mode, this pin can serve as the external-memory active-low write-enable output signal.
Also in serial host mode, this pin can serve as a general purpose input or output bit.

CS—Host Parallel Chip Select, Host Serial SPI Chip Select: Pin 18

In parallel host mode, this pin serves as the active-low chip-select input signal. In serial host SPI mode, this pin is used as the active-low
chip-select input signal.

RESET—Master Reset Input: Pin 36

Asynchronous active-low master reset input. Reset should be low at power-up to initialize the CS493XX and to guarantee that the device
is not active during initial power-on stabilization periods. At the rising edge of reset the host interface mode is selected contingent on the
state of the RD, WR and PSEL pins. Additionally, an autoboot sequence can be initiated if a serial control mode is selected and ABOOT
is held low. If reset is low all bidirectional pins are high impedance inputs.

SCDIO, SCDOUT, PSEL, GPIO9—Serial Control Port Data Input and Output, Parallel Port Type Select: Pin 19

In I

2

C mode, this pin serves as the open-drain bidirectional data pin. In SPI mode this pin serves as the data output pin. In parallel host

mode, this pin is sampled at the rising edge of RESET to configure the parallel host mode as an Intel type bus or as a Motorola type bus.
In Parallel host mode, after the bus mode has been selected, the pin can function as a general-purpose input or output pin.

EXTMEM, GPIO8—External Memory Chip Select or General Purpose Input & Output Number 8: Pin 21

In serial control port mode, this pin can serve as an output to provide the chip-select for an external byte-wide ROM. In parallel and serial
host mode, this pin can also function as a general-purpose input or output pin.

INTREQ, ABOOT—Control Port Interrupt Request, Automatic Boot Enable: Pin 20

Open-drain interrupt-request output. This pin is driven low to indicate that the DSP has outgoing control data and should be serviced by
the host. Also in serial host mode, this siganl intiates an automatic boot cycle from external memory if it is held low through the rising edge
of reset.

AUDATA2—Digital Audio Output 2: Pin 39

PCM multi-format digital-audio data output, capable of two-channel 20-bit output. This PCM output defaults to DGND as output until
enabled by the DSP software.