DV-620 (serv.man4). - Section 3 - IC function list - page 20-38 - Sharp DVD Service Manual (repair manual). Page 11

Pin No.

Pin name

Type

Direction

Function

117

Y/R/V

O

AO

Reset:

(DAC B)

Standby: 3-S

When the Decoder outputs the composite video, this line is Y
When the Decoder outputs RGB, this line is the Red output
When the Decoder outputs YUV, this line is the Red output

118

C/B/U

O

AO

Reset:

(DAC C)

Standby: 3-S

When the Decoder outputs the composite video, this line is C
When the Decoder outputs RGB, this line is the Blue output
When the Decoder outputs YUV, this line is the V output

115

CVBS/C

O

AO

Reset:

(DAC D)

Standby: 3-S

When the Decoder outputs any of the types of video, this line can be programmed to output either composite or C.

120

RSET

I

AI

Resistive load for gain adjustment of the DACs

123

VREF

I

AI

Voltage reference for gain adjustment of the DACs

110

DACDISABLE

I

I

Input

DACs disable input. High level force the DACs to float their outputs. Low level selects normal operation of the DACs.

112

COSYNC

3-S

O (p.d.)

Reset: output (low)
Standby: 3-S

Composite sync output. Active only when RGB analog output is selected. Otherwise, the signal is low.

Digital Audio Interface (9 pins)

Pin No.

Pin name

Type

Direction

Function

144

AMCLK

3-S

I/O (p.u.)

Reset: input
Standby: 3-S

Audio Master Clock input/output. 128, 192, 256 or 384 times the sampling frequency (programmable).

146

S/PDIF (AOUT4)

O

O (p.d.)

Reset: input
Standby: 3-S

S/PDIF transmitter output for digital coded or reconstructed audio data. Alternately can be used as a fifth audio
output. After RESET this pin outputs low level.

152

AOUT[3]

O

O (p.d.)

Reset: output (low)

151

AOUT[2]

Standby: 3-S

150

AOUT[1]

149

AOUT[0]
Serial outputs of digital stereo audio.

125

AIN

I

I

Input

Serial input of digital stereo audio.

153

ALRCLK

O

O (p.d.)

Reset: output (low)
Standby: 3-S

Digital audio left/right select output for the audio port. Square wave, at the sampling frequency.
Programmable polarity interpretation for input.

154

ABCLK

O

O (p.d.)

Reset: output (low)
Standby: 3-S

Digital audio bit-clock output. Data on AOUT and AIN is output or latched, respectively, with the rising or falling
(programmable) edge of this clock.

PLL/Clock Interface (6 pins)

Pin No.

Pin name

Type

Direction

Function

132

GCLK

I

I

Input

27.000MHz clock or crystal input for main processing clock generation.

129

GCLK1

I

I

Input

27.000MHz clock input for audio master clock generation. In normal operation must be connected to GCLK.

131

XO

O

AO

Output to a crystal that is connected to GCLK. If a crystal is not used at GCLK, XO must be left not connected.

134

PLLCA

AI/O

PLL Capacitor. In normal operation must be connected to a 47nF capacitor, of which the other node is connected to
GNDA.

127

PLLCFG[1]

I

I

Input

130

PLLCFG[0]

I

I

Input

PLL configuration inputs. Allowed to be changed only during RESET. In normal operation both pins must be
connected to GNDP.