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XL-MP100H
8 – 11
IC805 VHIHY57V16D-1: DRAM (HY57V16D)
IC805 VHIHY57V16D-1: DRAM (HY57V16D)
PIN
Terminal Name
Function
CLK
Clock
the system clock input. All other inputs are referenced to the SDRAM on the rising edge of CLK.
CKE
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will be one of the states
among power down, suspend or self refresh.
among power down, suspend or self refresh.
CS
Chip Select
Command input enable or mask except CLK, CKE and DQM.
BA
Bank Address
Select either one of bank during both RAS and CAS activity.
A0~A10
Address
Row address:RA0~RA10, Column Address:CA0~CA7
Auto-precharge flag:A10
Auto-precharge flag:A10
RAS,CAS,WE
ROW Address Strobe, Column
Address Strobe, Write Enable
Address Strobe, Write Enable
RAS, CAS and WE define the operation. Refer function truth table for details.
LDQM,UDQM
Data Input/Output Mask
DQM control output buffer in read mode and mask input data in write mode
DQ0~DQ15
Data Input/Output
Multiplexed data input/output pin.
VDD/VSS
Power Supply/Ground
Power supply for internal circuit and input buffer.
VDDQ/VSSQ
Data Output Power/Ground
Power supply for DQ.
NC
No Connection
No connection
V
DQ0
DQ1
V
SSQ
DQ2
DQ3
V
DDQ
DQ4
DQ5
V
SSQ
DQ6
DQ7
VDDQ
LDQM
/WE
/CAS
/RAS
/CS
A11
A10
A0
A1
A2
A3
V
DD
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
25
50pin TSOP ll
400mil x 825mil
0.8mm pin pitch
0.8mm pin pitch
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
33
32
31
30
29
28
27
26
V
SS
A4
A5
A6
A7
A8
A9
NC
CKE
CLK
UDQM
NC
VDDQ
DQ8
DQ9
VSSQ
DQ10
DQ11
VDDQ
DQ12
DQ13
VSSQ
DQ14
DQ15
V
SS
Refresh
Interval Timer
Self Refresh Counter
Address[0:10]
CLK
CKE
BA(A11)
CS
RAS
CAS
WE
UDQM
LDQM
Precharge
Row Active
Column Active
Address
Register
Register
Burst Length
Counter
Mode Register
Test Mode
I/O Control
Overflow
Column Addr.
Latch & Counter
512Kx16
Bank 0
Sense AMP & I/O gates
Column Decoder
Column Decoder
Sense AMP & I/O gates
512Kx16
Bank 1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
Refresh
Counter
State
Machine
Ro
w
A
ddr
.
Latch/Predecoder
Data
Input/Output
Buff
ers
Ro
w
Addr
.
Latch/Predecoder
Ro
w
Decoder
Ref
.
Addr
.[0:11]
A
u
to/Self
Refresh
Figure 10 BLOCK DIAGRAM OF IC
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