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SD-PX15H
8 – 15
IC3501 RH-iX3590CEZZ: Flash ROM (IX3590CE) (2/2)
Pin No.
Terminal Name
Input/Output
Function
40, 41
DQ5, DQ13
Input/Output
Data input/output: Data/command input, memory array, and status register during a Command User
Interface (CUI) write cycle. Data output during an ID code read cycle. When a chip is not selected or
output is disabled, the pin goes to the floating state. Data is latched internally in a write cycle. In the
byte mode, DQ8 - DQ15 are not used and DQ15 becomes address input (A-1).
Interface (CUI) write cycle. Data output during an ID code read cycle. When a chip is not selected or
output is disabled, the pin goes to the floating state. Data is latched internally in a write cycle. In the
byte mode, DQ8 - DQ15 are not used and DQ15 becomes address input (A-1).
42, 43
DQ6, DQ14
Input/Output
Data input/output: Data/command input, memory array, and status register during a Command User
Interface (CUI) write cycle. Data output during an ID code read cycle. When a chip is not selected or
output is disabled, the pin goes to the floating state. Data is latched internally in a write cycle. In the
byte mode, DQ8 - DQ15 are not used and DQ15 becomes address input (A-1).
Interface (CUI) write cycle. Data output during an ID code read cycle. When a chip is not selected or
output is disabled, the pin goes to the floating state. Data is latched internally in a write cycle. In the
byte mode, DQ8 - DQ15 are not used and DQ15 becomes address input (A-1).
44, 45
DQ7, DQ15
Input/Output
Data input/output: Data/command input, memory array, and status register during a Command User
Interface (CUI) write cycle. Data output during an ID code read cycle. When a chip is not selected or
output is disabled, the pin goes to the floating state. Data is latched internally in a write cycle. In the
byte mode, DQ8 - DQ15 are not used and DQ15 becomes address input (A-1).
Interface (CUI) write cycle. Data output during an ID code read cycle. When a chip is not selected or
output is disabled, the pin goes to the floating state. Data is latched internally in a write cycle. In the
byte mode, DQ8 - DQ15 are not used and DQ15 becomes address input (A-1).
46
GND
—
Ground: Connect all the ground pins.
47
BYTE#
Input
Byte enable: When BYTE# = VIL, the device enters the byte mode (x8). At this time, DQ8 - 14 pins
go into HighZ state and DQ15/A-1 becomes least significant address input (A-1). When BYTE# =
VIH, the device goes into the word mode (x16) and DQ15/A-1 pin becomes data input/output DQ15.
go into HighZ state and DQ15/A-1 becomes least significant address input (A-1). When BYTE# =
VIH, the device goes into the word mode (x16) and DQ15/A-1 pin becomes data input/output DQ15.
48
A16
Input
Memory address input: Address input for reading and writing. Addresses are latched internally dur-
ing a write cycle.
A1: least significant address input in byte mode (BYTE# = VIL),
data input/output DQ15 in the word mode (BYTE# = VIH)
A15- A19: main block selection address
A12- A19: boot/parameter block selection address
ing a write cycle.
A1: least significant address input in byte mode (BYTE# = VIL),
data input/output DQ15 in the word mode (BYTE# = VIH)
A15- A19: main block selection address
A12- A19: boot/parameter block selection address
48-LEAD TSOP
A15
A14
A13
A12
A11
A10
A14
A13
A12
A11
A10
A9
A8
A8
A19
NC
WE#
RP#
VCCW
WP#
RY/BY#
A18
A17
A17
A7
A6
A5
A4
A3
A2
A1
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
BYTE#
GND
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
GND
CE#
A0
BYTE#
GND
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
GND
CE#
A0
STANDARD PINOUT
TOP VIEW
12mm x 20mm
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Figure 8-15 BLOCK DIAGRAM OF IC
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