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SD-PX15H
8 – 14
IC3501 RH-iX3590CEZZ: Flash ROM (IX3590CE) (1/2)
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Pin No.
Terminal Name
Input/Output
Function
1-9
A15-A8, A19
Input
Memory address input: Address input for writing and reading. Addresses are latched internally dur-
ing a write cycle.
A1: least significant address input in byte mode (BYTE# = VIL),
data input/output DQ15 in the word mode (BYTE# = VIH)
A15- A19: main block selection address
A12- A19: boot/parameter block selection address
ing a write cycle.
A1: least significant address input in byte mode (BYTE# = VIL),
data input/output DQ15 in the word mode (BYTE# = VIH)
A15- A19: main block selection address
A12- A19: boot/parameter block selection address
10
N.C.
—
No connection: Not connected internally. (can also be connected)
11
WE#
Input
Write enable: Writing to the CUI and array block is controlled. Activated when WE# = VIL. Addresses
and data are latched on the rising edge of WE# pulse.
and data are latched on the rising edge of WE# pulse.
12
RP#
Input
Reset: It is activated and automatically reset internally when RP# = VIL. The device operates nor-
mally when RP# = VIH. When RP# = VIL, writing is prohibited and data is protected. After recovering
from the reset mode, the device enters the array readout status. Make sure to set VIL when turning
on the power.
mally when RP# = VIH. When RP# = VIL, writing is prohibited and data is protected. After recovering
from the reset mode, the device enters the array readout status. Make sure to set VIL when turning
on the power.
13
VCCW
Input
Block erase, full chip erase, word/byte write and lock bit configuration power supply: Memory data is
not changed when VCCW VCCWLK. Operations with improper voltage may cause malfunction or
breakage. When VCCW voltage is 12 ± 0.3 V, data can be rewritten up to 1,000 times per block.
When applying 12 ± 0.3 V to VCCW pin, total application time must be no longer than 80 hours.
not changed when VCCW VCCWLK. Operations with improper voltage may cause malfunction or
breakage. When VCCW voltage is 12 ± 0.3 V, data can be rewritten up to 1,000 times per block.
When applying 12 ± 0.3 V to VCCW pin, total application time must be no longer than 80 hours.
14
WP#
Input
Write protect: When WP# = VIL, the boot block is protected from writing and erasing. Even when
WP# = VIH, writing and erasing are prohibited if the block lock bit is set. For the parameter/main
block, writing and erasing are controlled by the block lock bit status regardless of WP#.
WP# = VIH, writing and erasing are prohibited if the block lock bit is set. For the parameter/main
block, writing and erasing are controlled by the block lock bit status regardless of WP#.
15*
RY/BY#
Output
Ready/Busy: The status of the internal Write State Machine (WSM) is sent. When VIL is supplied,
WSM is working (block erase, full chip erase, word/byte write, and lock bit configuration). When RY/
BY# = HighZ, WSM is waiting for the next command; word/byte write is not executed with block
erase suspended; word/byte write is suspended; or WSM is in the reset mode.
WSM is working (block erase, full chip erase, word/byte write, and lock bit configuration). When RY/
BY# = HighZ, WSM is waiting for the next command; word/byte write is not executed with block
erase suspended; word/byte write is suspended; or WSM is in the reset mode.
16, 17
A18, A17
Input
Memory address input: Address input for writing and reading. Addresses are latched internally dur-
ing a write cycle.
A1: least significant address input in byte mode (BYTE# = VIL),
data input/output DQ15 in the word mode (BYTE# = VIH)
A15- A19: main block selection address
A12- A19: boot/parameter block selection address
ing a write cycle.
A1: least significant address input in byte mode (BYTE# = VIL),
data input/output DQ15 in the word mode (BYTE# = VIH)
A15- A19: main block selection address
A12- A19: boot/parameter block selection address
19-25
A7-A0
Input
Memory address input: Address input for writing and reading. Addresses are latched internally dur-
ing a write cycle.
A1: least significant address input in byte mode (BYTE# = VIL),
data input/output DQ15 in the word mode (BYTE# = VIH)
A15- A19: main block selection address
A12- A19: boot/parameter block selection address
ing a write cycle.
A1: least significant address input in byte mode (BYTE# = VIL),
data input/output DQ15 in the word mode (BYTE# = VIH)
A15- A19: main block selection address
A12- A19: boot/parameter block selection address
26
CE#
Input
Chip enable: Control logic, input buffer decoder, sense amplifier of the device are activated when
CE# = VIL. When CE# = VIH, the device is not selected and power consumption is reduced to the
stand-by level.
CE# = VIL. When CE# = VIH, the device is not selected and power consumption is reduced to the
stand-by level.
27
GND
—
Ground: Connect all the ground pins.
28
OE#
Input
Output enable: Device output is controlled during a read cycle. Activated when OE# = VIL.
29, 30
DQ0, DQ8
Input/Output
Data input/output: Data/command input, memory array, and status register during a Command User
Interface (CUI) write cycle. Data output during an ID code read cycle. When a chip is not selected or
output is disabled, the pin goes to the floating state. Data is latched internally in a write cycle. In the
byte mode, DQ8 - DQ15 are not used and DQ15 becomes address input (A-1).
Interface (CUI) write cycle. Data output during an ID code read cycle. When a chip is not selected or
output is disabled, the pin goes to the floating state. Data is latched internally in a write cycle. In the
byte mode, DQ8 - DQ15 are not used and DQ15 becomes address input (A-1).
31, 32
DQ1, DQ9
Input/Output
Data input/output: Data/command input, memory array, and status register during a Command User
Interface (CUI) write cycle. Data output during an ID code read cycle. When a chip is not selected or
output is disabled, the pin goes to the floating state. Data is latched internally in a write cycle. In the
byte mode, DQ8 - DQ15 are not used and DQ15 becomes address input (A-1).
Interface (CUI) write cycle. Data output during an ID code read cycle. When a chip is not selected or
output is disabled, the pin goes to the floating state. Data is latched internally in a write cycle. In the
byte mode, DQ8 - DQ15 are not used and DQ15 becomes address input (A-1).
33, 34
DQ2, DQ10
Input/Output
Data input/output: Data/command input, memory array, and status register during a Command User
Interface (CUI) write cycle. Data output during an ID code read cycle. When a chip is not selected or
output is disabled, the pin goes to the floating state. Data is latched internally in a write cycle. In the
byte mode, DQ8 - DQ15 are not used and DQ15 becomes address input (A-1).
Interface (CUI) write cycle. Data output during an ID code read cycle. When a chip is not selected or
output is disabled, the pin goes to the floating state. Data is latched internally in a write cycle. In the
byte mode, DQ8 - DQ15 are not used and DQ15 becomes address input (A-1).
35, 36
DQ3, DQ11
Input/Output
Data input/output: Data/command input, memory array, and status register during a Command User
Interface (CUI) write cycle. Data output during an ID code read cycle. When a chip is not selected or
output is disabled, the pin goes to the floating state. Data is latched internally in a write cycle. In the
byte mode, DQ8 - DQ15 are not used and DQ15 becomes address input (A-1).
Interface (CUI) write cycle. Data output during an ID code read cycle. When a chip is not selected or
output is disabled, the pin goes to the floating state. Data is latched internally in a write cycle. In the
byte mode, DQ8 - DQ15 are not used and DQ15 becomes address input (A-1).
37
VCC
Input
Device power supply: When VCC? VLKO, the flash memory is protected from writing. Improper VCC
voltage may cause malfunction.
voltage may cause malfunction.
38, 39
DQ4, DQ12
Input/Output
Data input/output: Data/command input, memory array, and status register during a Command User
Interface (CUI) write cycle. Data output during an ID code read cycle. When a chip is not selected or
output is disabled, the pin goes to the floating state. Data is latched internally in a write cycle. In the
byte mode, DQ8 - DQ15 are not used and DQ15 becomes address input (A-1).
Interface (CUI) write cycle. Data output during an ID code read cycle. When a chip is not selected or
output is disabled, the pin goes to the floating state. Data is latched internally in a write cycle. In the
byte mode, DQ8 - DQ15 are not used and DQ15 becomes address input (A-1).
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