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SD-PX15H
6 – 25
Figure 6-25 SCHEMATIC DIAGRAM (12/22)
STA505
SWITCHING
AUDIO
POWER
AMP.
0.1
0.001
0.1
47/35
.1
MA111
MA111
4.7K
10K
MA111
4.7K
10K
MA111
100
0.001
0.001
4.7K(B)
8.2K
120K
20K
8.2K
120K
20K
120K
120K
4.7K(B)
1K
10/16
10/16
0.1
100
100
100
IX0498AW
100
0.001
47/16
0.001
0.1
100/50
6.8K
0.1
4.7K(B)
8.2K
120K
20K
8.2K
120K
20K
120K
120K
4.7K(B)
0.001
1K
10/16
10/16
0.1
100
100
100
IX0498AW
001
STA505
0.1
0.001
0.001
0.001
0.1
0.1
18P(CH)
100
0.82
2.2K
0.047
0.047
820
2.2K
820
680
680
150
150
680
680
150
150
6.8K
6.8K
6.8K
6.8K
6.8K
6.8K
0.82
0.047
0.047
2.2K
820
680
680
150
150
680
680
150
150
6.8K
6.8K
6.8K
6.8K
6.8K
0.01
820
2.2K
75K
75K
75K
75K
0.1
0.001
3.3K
100P(CH)
3.3K
10/10
10/10
75K
75K
47/16
0.001
0.1
3.3K
100P(CH)
3.3K
10/10
10/10
47/16
6.8K
6.8K
820
2.2K
0.047
0.047
0.1
100P(CH)
56P(CH)
0.001
0.1
100P(CH)
56P(CH)
6.8K
820
2.2K
820
0.047
0.047
2.2K
100K
100K
0.82
0.82
9
16
17
18
19
20
21
22 23 24
8
7 6 5 4 3
2
1
9
10
11
12
15
16
17
18
19
20
21
22 23 24
14
13
8
7 6 5 4 3
2
1
4
5 6
7 8 9
10 11 12
13 14
15 16 17 18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
1
2 3
5 6
7 8 9
10 11 12
13 14
15 16 17 18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
2 3 4
A+5V
A+5V
D+5V
FAULT
TH_WAR
TRI-STATE
PWR_DW
TH_WAR
FAULT
TRI-STATE
PWR_DW
DGND-AD
RESET
RESET
IN
11.2896
M
Hz
TH_WAR
FAULT
TRI-STATE
PWRDW
IN1B
IN1A
IN2A
IN2B
CONFIG
IBIAS
VDD
VDD
GND-Reg
GND-Clean
Vss
Vss
NC
OUT1A
OUT1A
GND1A
GND1B
Vcc1A
Vcc1B
OUT1B
OUT1B
OUT2A
OUT2A
Vcc2A
GND2A
GND2B
Vcc2B
OUT2B
OUT2B
NFL2(-)
NFL1(+)
GNDA
L-CH
Vref
R-CH
V
ref
R-CH
IN
L-CH
IN
RESET
VDDL
GNDD
OUTL(+)
OUTL(-)
OUTR(-)
OUTR(+)
VDDR
VDDX
XI
SUBWOOFER IN
REAR
L-CH_IN
REAR
CENTER
AGND
R-CH_IN
AGND
SUBWOOFER+
SUBWOOFER-
CENTER-
CENTER+
MCK
GNDX
XO
XI
VDDX
VDDR
OUTR(+)
OUTR(-)
OUTL(-)
OUTL(+)
GNDD
VDDL
VDA
RESET
L-CH
IN
R-CH
IN
R-CH
Vref
L-CH
Vref
GNDA
NFR2(-)
NFL1(+)
NFL2(-)
NFR1(+)
TEST
REAR
R-CH_+
REAR
R-CH_-
REAR
L-CH_-
REAR
L-CH_+
GND-SUB
OUT2B
OUT2B
Vcc2B
GND2B
GND2A
Vcc2A
OUT2A
OUT2A
OUT1B
OUT1B
Vcc1B
Vcc1A
GND1B
GND1A
OUT1A
OUT1A
NC
VccSign
VccSign
Vss
Vss
GND-Clean
GND-Reg
VDD
VDD
IBIAS
CONFIG
IN2B
IN2A
IN1A
IN1B
PWRDW
TRI-STATE
FAULT
TH_WAR
1
1
0.001
0.001
0.001
1
1
9
10
11
11
10
12
13
13
12
14
14
15
4
3
1
1
3
4
5
6
7
8
5
6
9
10
12
11
7TH ORDER
∆Σ
MODULATION
CONVERSION LSI
7TH ORDER
∆Σ
MODULATION
CONVERSION LSI
R-CH OUTPUT
OFFSET
ADJUSTMENT
OFFSET
ADJUSTMENT
L-CH OUTPUT
OFFSET
ADJUSTMENT
OFFSET
ADJUSTMENT
R-CH OUTPUT
OFFSET
ADJUSTMENT
OFFSET
ADJUSTMENT
L-CH OUTPUT
OFFSET
ADJUSTMENT
OFFSET
ADJUSTMENT
CNP603
6 - 22 3 - B
TO TERMINAL PWB
14
2 - A
Y PWB
1-BIT AMP. PWB-C
+B
+B
+B
+B
+B
+B
+B
+B
+B
+B
VDA
+B
+B
+B
+B
The numbers
1
to
6
,
11
,
12
are waveform numbers shown in page 5-2.
RA202
RA204
RA208
RA206
VRA202
RA210
CA202
VRA201
RA201
RA209
RA207
RA205
CA201
RA203
CA203
CA205
CA206
CA204
RA272
CA262
CA261
CA280
CA363
CA379
RA314
RA312
RA213
RA211
CA265
CA264
CXA201
CA268
CA267
CA211
CA266
ICA201
RA262
RA263
DA264
CA269
CA270
RA215
RA217
RA218
RA216
A276
A274
DA265
CA273
CA272
RA278
ICA202
CA210
CA208
RA276
RA222
RA274
RA220
RA228
RA226
RA239
RA240
RA237
RA238
RA235
RA236
RA234
RA233
CA209
CA207
RA231
RA229
RA275
RA221
RA219
RA273
RA225
RA227
LA201
CA215
CA217
CA219
LA203
CA216
LA204
CA218
CA220
LFA202
BIA104A
BIA104C
CNSA104
LFA302
LA304
LA302
CA320
CA318
CA316
CA377
LA303
CA319
LA301
CA315
CA317
LFA301
RA325
RA327
RA329
RA331
RA339
RA340
RA337
RA338
RA335
RA336
RA333
RA328
RA326
RA376
RA374
CA310
CA308
RA322
CA360
RA330
RA332
RA373
RA375
CA309
CA307
RA321
RA319
ICA302
DA365
CA376
CA375
CA374
CA373
CA372
RA378
CA413
CA369
CA370
RA362
RA363
DA364
RA315
RA317
RA316
RA318
CA368
RA361
CA367
CA366
CA364
CA365
RA313
RA311
ICA301
CA362
CA361
CA380
RA372
CA303
CA305
CA306
CA304
RA302
RA308
RA310
RA306
VRA302
CA302
RA304
VRA301
RA307
RA305
RA303
RA301
RA309
CA301
RA334
LFA201
LA202
FM SIGNAL
3
4
1
2
5
6
11
12
3
4
1
2
5
6
11
12
7
8
9
10
11
12
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